PDP-9 Restoration Blog Starting 2019


2/16/19
Moved to the new Lab space.

3/2/19 Hours: 40412.4
We powered up the PDP-9 for the first time in the new lab space. Bit-9 is stuck on in all of the registers so that is the first thing to fix.

3/10/19
We made a longer power cord out of 12-3 SOO cord.
We measured the power consumption at 11A @ 120VAC, so it will $0.30/hour to run the CPU.

We swapped the B131 modules in slots A21 and A23, these are the Adder modules for bits 8 & 9.
The stuck bit moved to bit 8, so we know that the B131 that came out of slot A23 is defective.
We don't have a spare, so we will need to repair it.

3/16/19
The A BUS input on pin S was at -.011V (logic 0) and the other boards were at -3.46 (logic 1).
The SUM output on pin V was at -.3.53V (logic 1) and the other boards were at -0.11 (logic 0).

We measured the input and output voltages on the misbehaving B131 FlipChip, and on the two working neighbors.
Right away we could see that the output voltage was not correct on the broken B131, which explains the stuck bit-9.

The Adder circuitry in the PDP-9 is very fast (for its time), very complicated, and mostly analog.
The internal circuitry has four possible current/voltage levels depending on the state of the four inputs. 

We made a benchtop test setup for the B131 so we could manipulate the input signals and measure the output signals.
Then we compared the behavior of a good B131 to the bad B131.
After a few hours of pondering the schematic to see how it works we were able to devise tests that would show if each of the individual transistors were working correctly.
Eventually we determined that Q4, a 2N3669 transistor was not working at all.
We replaced it with a New Old Stock part, and now the B131 is working again, and the stuck bit-9 is gone.
Alex is making an LT Spice model of this FlipChip so we can better understand how it works.

Click on the image of the B131 Adder for a larger view.

When running at the slowest possible speed the PDP-9 will run two JMP instructions.
Otherwise the behavior is inconsistent, and the Deposit & Examine doesn't always work on the first try.
This sounds like timing issues, so we need to go through the procedures in the System Adjustment manual.

3/17/19
We did some more debugging on Sunday to determine what instructions work and found that the JMP instruction goes to the wrong address.
After some digging we found a stuck bit-17 in the AC register.
We swapped the B213 module on slot C39 that holds that AC register bit, the B169 in slot A38 that gates the output to the A BUS, and the B169 in slot B38 that gates the input, but did not see any changes.
We have spare B213 and B169 modules so this should be an easy fix.

3/23/19
Well, the fix was not so easy.
After several hours of boards swaps and debugging we eventually found a bad B213 FlipChip in slot C39.
This FlipChip provides bits 16 & 17 in the AC register and was the cause of the stuck bit 17.

After this repair the system ran MAINDEC-9A-D1AA-D PDP-9 Basic Memory Checkerboard Test for a few minutes and then halted at location 223.
This is the correct behavior when it detects a memory error.

The DEC-9A-H0AA-D PDP-9 System Adjustment Manual describes a procedure to adjust:

  • Clamp and Slice voltages in the Core Memory
  • MA Setup, Stagger Delay, Strobe Delay, Pause Delay, and the Write Delay timing in the Core Memory
  • Current Start Delay, Start Delay, Width Delay, Loop Delay, Strobe Start Delay, CLR Position Delay, and Current Delay in the Control Memory
  • And check other system timing and pulse width values
We will run through the System Adjustment procedure And then try it again.
We will also run the MAINDEC-9A-D01A-D_Instruction_Test_Part_I_Nov67 and MAINDEC-9A-D02A-D_Instruction_Test_Part_II_Nov67 to make sure that all of the instructions are working.

3/24/19
We fiddled with the system a little before we made all of the adjustments.

We ran MAINDEC-9A-D1AA-D PDP-9 Basic Memory Checkerboard Test for a few minutes and then halted at location 223.
C(AC) = 000000 = Memory Address where the error occurred
Press CONTINUE C(AC) = 200000 = Correct data word
Press CONTINUE C(AC) = 740044 = Incorrect data word
Press CONTINUE C(AC) = 000000 = Pattern control word, should be a 000000 or a 777777

Hopefully if will behave better after we adjust everything.

3/30/19
We decided to run MAINDEC-9A-D01A Instruction Test Part 1 to make sure that the processor is fully functional.
The diagnostic failed immediately at address 000575, which is E83.
After reading through the source code we restarted the diagnostic at 000551 and single stepped the processor.
This test clears the AC and Link, compliments the Link, and rotates the Link bit left through all of the AC bits.
It failed when it tried to rotate the bit from bit-12 to bit-11.
We swapped the B169 modules between slots B22 and B26 and the error moved to bit 9/10.
We put the B169 from slot B26 back in B22 and put a replacement B169 in slot B26.

Instruction Test Part 1 now runs OK. 
In the video below we configured the PDP-9 in Single Instruction mode, locked Continue on, enabled Repeat, and set the repeat speed to the minimum.
This causes the machine to run a few instructions per second so you can watch what it is doing.
The upper register on the right shows the contents of the memory that is being accessed and usually contains the instruction being executed.
The lower display is set to show the AC register, part of the machine being tested.

The PDP-9 running Instruction Test 1 very slowly


We were able to successfully run other diagnostics, but not at full speed.

4/6/19
We spend most of the time wiring new AC outlets for the PDP-9, so only a little debug time.
The core memory seems to be working OK even after we fiddled with the voltage and delay settings.
The core memory still needs the final tuning.

We found that the JMP instruction just goes to the next sequential address instead of to the address in the instruction.
That will be our next debuging project.

We also noticed that one of the G882 FlipChips is missing from the TC02 DECtape controller.
We will need to find a replacement before we can try reading/writing DECtapes.
A very generous Anders Sandahl sent us a G882 from his collection.

4/13/19
We did a lot of studying of the circuitry that makes up the Control Memory, known as microcode on a modern computer.
We determined the correct sequence of events, and made a plan to check the Control Memory sequence and why it wasn't executing Control Word 74 for the JMP instruction.

Click on the image for a larger view.

After a lot of 'scope work we determined that we could actually see the signals go active in the Read Only Program memory and could verify which Control Memory words were being executed.
In the 'scope image above the yellow trace is CM CURRENT signal that cause the contents of the Control Memory to be read.
The green trace is the CM STROBE that latches the data from the Control Memory. The signal going positive and negative is actually a DEC standard pulse.
The purple trace CMP7 signal and the blue trace CMG4 are the address lines for the Control Memory that select the Control Word for the JMP instruction.
Oops, you can see in the third sequence where purple goes up and blue goes down that Control Word 74 is being executed.
So much for the out of sequence Control Memory theory.

The last of the four Control Word sequences in the 'scope image is 10, BGN, where it gates the PC into the MB, and waits for the core memory to fetch the next instruction.
The processor will stop at this point if the Single Instruction switch is turned on, which we did.

Now that we knew that Control Word 74 was being executed we verified that all of the bits in the Control Word were being latched.
We quickly found that the PCI bit that latches the new memory address into the program counter was inactive.
That explains why it would not JMP.
We replaced the B213 Jam Flip-Flop module in slot D21 and now the JMP instruction is working again.

Time to go back to adjusting and tuning the core memory and processor, and then on to connecting and debugging the TC02 DECtape controller.

4/20/19
last week we found that one of the Control Memory Flip-Flop FlipChips was defective and replaced it with a spare.
That fixed the PCI (Program Counter In) Control Memory signal, and the JMP instruction.
Unfortunately it looks like we broke many of the other instructions in the process of fixing the JMP instruction.
Each of the B213 modules Flip-Chips, like the one that we replaced, contains two Flip-Flops.
Replacing the B213 in slot D21 fixed the PCI bit, but now it looks like the other half of the FlipChip is broken, and that is affecting the PCO Control Memory signal.
Having a misbehaving PCO (Program Counter Out) signal would explain why many of the other instructions are misbehaving.
We have a few more untested B213 modules we can try, and then it will be time to fix the pile of broken B213 modules we have.

Click on the image of the B213 for a larger view.

We don't have a FlipChip tester that is capable of testing the B/R/S negative logic modules, so we will need to make a bench test setup.
We have a connector module that will hold the FlipChip, and a 3x voltage power supply that we can use to power it.
All we will need for testing is a signal source for a -3V->GND fast pulse for the strobe, and a logic level for the data input.
We even have NOS 2N3009 and 2N3639 transistor for replacements.

4/20/19
We installed the G882 FlipChip Anders Sandahl donated in the TC02 DECtape controller.
We borrowed two TU50 DECtape drives from the PDP-8/I. It still has three TU50 drives.
We installed both drives above the TC02 controller in the expansion cabinet and cabled them to the TC02 controller.
We still need to borrow a 779 power supply from the PDP-8/I and also install it in the expansion cabinet.
The 779 power supply will power the TC02 controller and both TU50 DECtape drives.

The bottom controller is the TC-59 for the TU20 1/2" 7-track magnetic tape drive.
The upper controller is the TC02 for the DECtape drives.
The lower of the TU50 DECtape drives is older and has an extruded aluminum frame instead of a cast frame.

5/5/19
We spent the day chasing the JMP instruction not working issue.

We checked the system timing using the procedures in the DEC-9A-H0AA-D PDP-9 System Adjustment Manual.
All of the timing measurements were within specifications.

We checked all of the microcode bits in each microword and found that the PCI flip-flip was not being set in microword 74.
This will prevent the address from the JMP instruction from being transferred to the PC register and prevent the JMP from going to the correct address.

The PCI flip-flip was being set in microword 21, so we knew that the transformer for the PCI signal on the G920 module was OK.
The MBO flip-flop was being set in both Microword 21 and 74, so we knew that the microcode was being executed in the right sequence.

In this 'scope image you can see that the PCI flip-flip was being set in microword 21m and not in microword 74.
It looks like the CMSL13 signal from the G920 transformer is near ground at microword 21, but is near -2V in microword 74.
We think that this is why the PCI flip-flop is not being set.
It will take a lot of investigating to determine why the PCI flip-flop is not being set.

5/12/19
After pondering the Microcode problem for a week we spent an afternoon verifying that the microcode sequence is what we expected.
An instruction starts with Microword 10, then 21, then 12, then it decodes the instruction and with the JMP goes to 74, and back to 10.
The processor will stop after Microword 10 if Single Instruction mode is on.

Click on the image for a larger view.
Lots of 'scope and Logic Analyzer probes on the Control Memory.

Microword 10 was executed before the processor stopped because we had the Single Instruction switch turned on.
We started with Microword 21, then went to 12, then to 74, then to 10, and stopped again.
This sequence shows that the complex logic for determining the next microword in the sequence is working correctly.

We added the CMP 2 (yellow) and CMG 1 (light blue) signals that drive the "21" wire for microword 21.
The purple trace shows the CMSL signal for the PCI microcode bit as it comes from the G920 flipchip.
The state of the CMSL signal is latched when the CM STROBE signal goes high.
In this case the first time the CM STROBE A signal went high the PCI flip-flop was set.
The next time the CM STROBE A signal went high the CMSL 13 signal was low so the PCI flip-flop was cleared.
This is good to see and means that the PCI transformer on the G920 board and the PCI flip-flop are OK.

We changed the yellow and light blue probes to the CMP 7 and CMG 4 signals that drive the "74" wire for the JMP instruction.
The third time the CM STROBE A signal went high the purple CMSL 13 signal should have been high and caused the PCI flip-flop to set.
You can see that the CMP 7 signal went to ground and the CMG 4 signal went to -15V so the drive current for the "74" wire was available.
We didn't see a pulse on the CMSL 03 for MBO, CMSL 18 for LI, or for CMSL 21 for DONE when the "74" wire wa activated.
This leads us to believe that there is a problem with one of the steering diodes or a wire connection on the G920 microcode board.
We will test and hopefully repair the G920 next week.

5/18/19
We finally found the problem with the PDP-9 Processor.
One of the diodes on the G920 Control Memory board had a voltage drop of 1.1V where it should have been about 0.65V.
This slight difference caused the current flowing through the wire for Microword 74 for the JMP instruction to be a little low, and it didn't set any of the microcode bits for that Microword.
The Program Counter didn't get updated with the new target address, so the JMP never happened.

Click on the image for a larger view.

Click on the image for a larger view.
The fourth diode from the top was defective.
The third diode from the top looks like it is cracked, so that one will likely fail too.


The G920 board holds all of the Microcode that controls how the processor behaves.
When a Microword is selected one of the 64 possible wires is connected to ground at the left side of the board, and to -15V on the right side.
This creates a magnetic field in the 36 transformers, and the direction of the magnetic field is determined by the wire being routed through the right or left side of the transformer.
When the -15V is disconnected, the magnetic field collapses, much like in an ignition coil, and it induces a ground or -4V signal in the secondary side of the transformer.
This signal is captured by Jam Flip-Flops for 200nS, and then the cycle starts again.

We don't have a schematic or a BOM for this board so debugging was a challenge.
We found that most of the diodes on the G920 had a voltage drop of 0.65V, but a few had a voltage drop of 0.76V.
These are also candidates for replacement.
We had a selection of diodes in our spares and decided that the 1N4149 was the best fit for this application.

The system now passes Instruction Test 1, Instruction Test 2, the JMP, ISZ, and JMS tests, and the Basic Memory Checkerboard.
It reports a few errors during the Memory Addressing test.
We still need to do the final timing and voltage tuning for the processor and memory, so hopefully that will fix the memory problem.

Instruction Test 1


Instruction Test 2


Basic Memory Checkerboard


TTY Test


Finally we will be able to connect the TC02 DECtape controller and the TU55 DECtape drives and start debugging those parts.
Eventually we will get an OS running from DECtape. We could even think about making an emulator for the RS09 disks!

5/19/19
Now that the processor is running again, we tried to finish the Core Memory tuning.

Click on the image for a larger view.
This shows the Core Memory sense strobe in yellow and a composite of many memory reads in aqua.
This is the same as Figure-7 in the PDP-9 System Adjustment manual for adjusting the Stagger Time.

One of the final adjustments is setting the Slice Voltage in the Core Memory.
You run the Extended Memory Checkerboard Maindec, flip a switch to power some of the FlipChips in the Memory Controller from the +10V margin voltage, and then adjust the +10V margin voltage up and down until the diagnostic reports errors.
Then you fiddle with the Slice Voltage setting until the amount you increase and decrease the +10 Margin Voltage to cause errors is symmetric.
In this case adjusting the Margin Voltage all the way up or down did not cause any memory errors.
We need to determine if the Margin Voltage is actually getting to the Memory Controller FlipChips.

5/25/19
The PDP-9 System Adjustment manual says to turn on Margin Switch 7, run the Memory Checkerboard, set the Margin Power Supply to +10V, and adjust the +10V up and down until the diagnostic reports errors.
We did that, but never saw memory errors reported.

We didn't know if the Margin power supply was working correctly so we opened the Memory fan housing that also contains the Margin switches and PCB.
We traced the path of the +10V, and -15V Margin power from the diagnostic control panel, through the wire harness to the switch panel.
We then traced the power through Margin switch 7, through the fuses, to the flipchips that send the power to the Memory Controller.
We then traced the wire-wrap wires that supply the power to just a small selection of flipchips.

Once we knew which flipchips were powered from Margin switch 7 it was rather easy to find pages in the schematics (MC70-B-17) that showed which flipchips were powered from which Margin switches.
In this case Margin switch 7 supplies a reference voltage to pin D of all 18 of the the G009 Sense Amplifiers.
Other Margin switches supply the +10V and -15V power to pins A & B of the G009s.
We will need to verify that the +10V margin voltage on on D of the G009s is being adjusted in a wide range.

5/26/19
We went through the Slice Level Setup procedure in section 2.2.3.7 of the System Adjustment Manual.
We connected a DVM to pin D of the G009 Sense Amplifiers to verify that the +10MC reference voltage was really changing when we adjusted the +10V Margin Voltage.
We adjusted the +10MC voltage on pin D of the Sense Amplifiers +/-7V from the nominal +10V while running MAINDEC-9A-D1BA-D PDP-9 Extended Memory Checkerboard Test.
No memory failures were observed while adjusting the +10MC voltage.
We should have seen memory errors which would have caused us to tune the Slice Voltage.
Oh well, no memory errors is a good thing.

We ran MAINDEC-9A-D1FA-D PDP-9 Extended Memory Address Test without errors.

We ran MAINDEC-9A-D7AD-D PDP-9 Basic Exerciser.
Since we haven't fixed the paper tape punch yet, it got stuck looking for the status of the punch.
We put NOP instructions in place of the JMP instructions were it was looking for the paper tape punch status, and it runs OK.

6/1/19
Alex is working on LT Spice simulations for the G008 and G009 modules in the Core Memory.
Today we will capture real Core Memory Sense Amplifier signals using our fancy Rigol 'scope, and save them as a CSV file.
We can import the CSV file into LT Spice and use it in the simulations.

After a lot of reading of manuals and Alex studying the G009 schematics we found that when switch #7 is on, the +10 Margin input can be varied +/-10V.
We originally thought that the +/-7V value in the System Adjustment Manual was the limit for the Margin voltage.
The +/-7V is actually the range which the Margin voltage should be able to be adjusted without causing memory errors.
We will rerun the MAINDEC-9A-D1BA-D PDP-9 Extended Memory Checkerboard Test and vary the +10 Margin through the whole range of +/-10V.
Then we can tune the Slice Voltage to make the Margin that causes memory errors symmetric.

We adjusted the +10 Margin Voltage to the Sense Amplifiers through the range of 2V to 20V.
At the high end of the range there were infrequent errors on bit-8.
We swapped the G009 Sense Amplifiers for bit-8 and bit-9, but it didn't make any difference.
There is a Digit Driver board for each bit, so we swapped the board for bit-8 and bit-9, but it didn't make any difference.
We decided to leave the Slice Voltage adjustment as it is, and declare it fixed.

Next we can mount and wire the power supply to the TC02 DECtape controller and the TU55 DECtape drives.
If we get through that, we can try some of the TC02 diagnostics and see if the controller responds.

6/2/19
We measured the output voltages from the G008 Slice Control so Alex can simulate the G009 Sense Amplifier.
When Halted, Pin H Slice: 5.50V, Pin M 1st Clamp: -11.23V, Pin N: 2nd Clamp: -8.95V.
When Running Checkerboard, Pin H Slice: 5.53V, Pin M 1st Clamp: -11.08V, Pin N: 2nd Clamp: -8.80V.

We inventoried the FlipChips in the TC02 DECtape controller
Missing:
  • A10, R002, Installed unknown condition R002
  • B10, S123, Installed unknown condition slower R123
  • E17, S203. Installed unknown condition slower R203
  • D14, S127, Holds an S107, need to compare to other TC02s (Looks like this is correct and the error in the documentation was fixed in later versions)
  • D19, empty, board is in C19
  • D20, empty, board is in C20
  • D24, R113, Installed unknown condition R113
  • D28, S202. Installed unknown condition slower R202
  • E17, S203. Installed unknown condition slower R203
  • E30, S002, Installed unknown condition R002

6/8/19
Anders will trade an RK05 blower motor that I have for the missing S modules for the TC02 DECtape controller.
Much easier to put the right flipchips in instead of changing resistors on the R modules to convert them to S modules.

Click on the image for a larger view.
We made an LT Spice simulation of the G008, G008, and G010 FlipChips so we can understand how the core memory works.
The two signals in the top pane are the sense wire outputs from the bottom 4k field of core memory.
The red signal in the bottom pane is the output from the sense amplifier, and the grey is the strobe that causes the data to be latched.
Other than an enable signal not working yet, the simulation is doing what it is supposed to.
It is pretty amazing that the sense amplifier can extract good data from the noise on the sense wire.
The input signals to the the LT Spice simulation is actual sense wire data from the PDP-9 captured with the Rigol 'scope.
Newer versions of computers use a monolithic integrated circuit sense amplifier that replaces the complete G009 FlipChip.

6/15/19
We received S series FlipChips from Anders to fill the empty slots in the TC02.

We wired the DC power to the TC02 DECtape controller and the two TU55 DECtape drives that we recently installed in the PDP-9 I/O cabinet.
We were not sure that the power supply for the TC59 that was already installed in the cabinet had enough output to also power the TC02 DECtape controller, and two TU55 DECtape drives.

Click on the image for a larger view.
When we first powered on the cabinet the +10V and the -15V from the power supply would not go to up to the normal voltage range.
I was quite close to the wiring while checking the voltages and then this electrolytic capacitor blew with a big bang!
The voltages then went to and acceptable range, so we knew where all the power was going.
The bridge rectifier on the power supply is getting quite warm, so we will replace the power supply with a larger one.

Click on the image for a larger view.
We still need to make ribbon cables to connect the indicator panel to the TC02 controller.
Without the cables installed all of the indicators should be on.
It looks like we have some bad connections, and possibly bad transistors on the indicator panel to debug and repair.

After we get the wiring completed we can see if the TC02 will talk to the PDP-9.
The TC02 is very similar to the TC01 DECtape controller that is in the PDP-8/I, so we are familiar with how it works and how to debug and repair it.

Once we get the TC02 controller and one of the TU55s drives working we will need to make a PDP-9 Advanced Software System Keyboard Monitor System DECtape and see if it will boot.
We will use the Dave Supnick's SIMH PDP-9 simulator to Sysgen an ADSS DECtape image to match our PDP-9's configuration.
Then we can use a PDP-8/e with a TC8E DECtape controller to write the PDP-9's ADSS DECtape.
Maybe, just maybe, we can get ADSS to run on the PDP-9.

To-Do:
The system was disassembled for shipment and needs to be reassembled. (Done)

Find the two I/O cables to connect the TC59 to the PDP-9. (Don't have them. Maybe we can get some from the LCM)
If we don't have the cables we might be able to use seven cables from a PDP-8 or borrow some from another PDP-9/10/15 collector.
 
There is some unconfirmed information that when this system was in its last days of service they had problems with the ROPE memory for the microcode.
There a rubber sheet that compresses the "E" cores together. We will need to replace it.
We have several spare ROPE memory boards. We have no idea if they are good, or what microcode is programmed.
 
We have two spare 8k core stacks if we find problems with the core in the system. (Didn't, works OK)
 
We were also told that when someone was trying to fix the system they pulled modules while the power was still on.
That may make it challenging to revive this system.
This system uses some of the same transistor only R series Flip-chips as the PDP-8/S so we have some spares for the modules.
It also uses quite a bit of the faster B series modules. We have just a few spare B modules.
 
The rough plan:
Reform the capacitors in the 709 power supply for the processor and test the power supply. (Done)
Reconnect the I/O cables for the paper tape reader/punch. (Done)
Find and connect the Teletype interface cable. This is actually on the PDP-11/23 that was connected to this system.
Power up the system and see what works. (Done)
There was some discussion that many of the light bulbs in the front panel were burned out.
    (All of the Register, Memory Buffer, and Interrupt lights work.) 
Reform the capacitors in the TU20 power supply and test the power supply. (Done)
Power up the TU20 and see what works. (Done)
The tape drive uses vacuum columns so it may be a significant challenge to get it working. 
Reform the capacitors in the TC59 power supply and test the power supply. (Done)
Connect the TC59 tape controller to the I/O section of the PDP-9 and to the TU20. (Done using borrowed PDP-8 I/O cables)
Debug the TC59 and the TU20. (In process)

Wire the DC power to the TC02 DECtape controller and connect the I/O cables between the processor and the TC02.
See if the TC02 responds to any IOT instructions.
Try the TC02 diagnostics.
Install a TU55 in the rack with the TC02 and TU59.
See if the DECtape works.

Once we get a DECtape working we can make an OS DECtape.
If the PDP-9 actually runs the OS, it will be the only one on the planet that can.

The instructions tested so far are:
CLA    Works OK
CLC    Works OK
CLL    Works OK
CLOF   Turns the CLK light off.
CLON   Turns the CLK light on.
CMA    Works OK
CML    Works OK
DAC    Works OK
DZM    Works OK Fixed on 3/23/13
HLT    Works OK Fixed on 3/23/13
IOF    Turns the PIE light off.
ION    Turns the PIE light on.
IZS    Works OK Fixed on 3/16/13
JMP    Works OK Fixed 3/10/13, Fixed again 5/18/19
LAC    Works OK
LAS    Works OK
NOP    Works OK
RAL    Works OK
RAR    Works OK
RTL    Works OK
RTR    Works OK
STL    Works OK

Maindec Diagnostics
MAINDEC-9A-D0BA-D ISZ Test, 5/18/19
MAINDEC-9A-D0CA Memory Address Test, 5/18/19 (Failed with a few errors)
MAINDEC-9A-D0DB-D-JMP Self Test, 5/18/19
MAINDEC-9A-D0EA-D JMP Y - Interrupt Test, 5/18/19
MAINDEC-9A-D0FA-D JMS Y TEST, 5/18/19
MAINDEC-9A-D01A-D Instruction Test Part 1, 5/18/19
MAINDEC-9A-D02A-D Instruction Test Part 2, 5/18/19
MAINDEC-9A-D1AA-D PDP-9 Basic Memory Checkerboard Test, 5/18/19
MAINDEC-9A-D1BA-D PDP-9 Extended Memory Checkerboard Test, 5/26/19
MAINDEC-9A-D1FA-D PDP-9 Extended Memory Address Test, 5/26/19
MAINDEC-9A-D2BA-D PDP-9 TTY Test, 5/18/19
MAINDEC-9A-D7AD-D PDP-9 Basic Exerciser (no punch or tape reader), 5/18/19


The boards replaced in the PDP-9 processor so far are: 

B131 Adder in slot A23, replaced Q4, 2N3669, 3/17/19
B169 Inverter (Multiplexor) in slot B26 of the processor with a spare
B310 Delay Line in slot EF29 of the processor with a spare, and again with a repaired module 
B213 JAM Flip-Flop in slot H33 of the processor with a spare, 2/2/13
B213 JAM Flip-Flop in slot C39 of the processor with a spare
B213 JAM Flip-Flop in slot C18 of the processor with a spare
B213 JAM Flip-Flop in slot C35 of the processor with a spare, and again with a spare
B213 JAM Flip-Flop in slot D20 of the processor with a spare
B213 JAM Flip-Flop in slot D21 of the processor with a space 4/13/19
B213 JAM Flip-Flop in slot D27 of the processor with a spare
B213 JAM Flip-Flop in slot D28 of the processor with a spare
B213 JAM Flip-Flop in slot H33 of the processor with a spare
B213 JAM Flip-Flop in slot E20 of the I/O controller with a spare
B310 Delay Line in slot EF29 of the processor with a spare 
B360 Adjustable Delay Line in slot D33 of the Core Memory with a spare
G219 Memory Selector in slot AB09 of the Core Memory with a spare 
G219 Memory Selector in slot HJ24 of the Core Memory with a spare 
G920 Repaired, and repaired again. 05/18/19 Replaced a diode with a 1N4149 for Microword 74
R111 Diode Gate in slot H23 of the processor with a spare
R123 Diode Gate in slot D15 in the I/O controller.
R401 Clock Flip-Flop module in slot KD09-E03 of the I/O controller with a spare. 
S205 Dual Flip-Flop module in slot KD09-D07 of the I/O controller with a lower drive R205 spare. We need to repair the S205 and put it back in the system.
S603 Triple Pulse Amplifier in slot J23 with a spare. Diode D42 on the original conducted in both directions.

The boards replaced in the TU20 Tape Drive so far are:
 
2N1304 transistor in the EOT circuit on the Photosense Amplifier in the tape transport.
G287 Write Driver in slots A02-A06, replaced 2x 2N3500 transistors for tracks B, 8, 2, and Parity. Some of the diodes on theses modules have small cracks.
R113 Diode Gate in slot B20 with a spare.
R123 Diode Gate in slot B17 has poor drive to pin P. Working OK, but should be checked further. The R123 Diode Gate in slot B17 was actually an R203 flip-flop. It was replaced with the correct spare.
R203 Triple Flip-Flop in slot B27 with a spare.
R205 Dual Flip-Flop in slot B04 with a spare.
R205 Dual Flip-Flop in slot B05 with a spare.
R302 Dual Delay in slot B09 with a spare. Set trimpots to the same values as on the original.
R302 Dual Delay in slot D29 with a spare. Set trimpots to the same values as on the original.
R303 Integrating One-Shot in slot A21, replaced the open Trimpot.
R401 Clock module in slot A15 with a spare
R602 Pulse Amplifier in slot B13 with a spare.
R602 Pulse Amplifier in slot B16 with a spare.
R603 Pulse Amplifier in slot A09 with a spare.
W501 Schmitt Trigger in slot C10 with a spare.
W501 Schmitt Trigger in slot D09 with a spare.

The boards replaced in the TC59 Tape Controller so far are:
 
R602 Pulse Amplifier in slot A21 with a repaired module.
W640 Pulse Amplifier in slot F22, replaced R17, Q8, and Q9.
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