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2/26/11
We pulled the G785 module out of the backplane. This disconnects the power supply from the backplane. We connected a Variac between the AC power source and the 8/L and slowly, over the course of hours, increased the AC voltage to the 8/L power supply. The voltages looked OK, so we put the G785 back in the backplane and powered it on at full AC voltage. After a few minutes smoke poured from the rear transformer in the power supply. Another 8/L owner reported the same smoke and found a shorted power diode in his power supply. We have another 8/L system that is in poor condition because rodents were living in it. The power supply looks OK, so we can try the power supply in the complete system next week. 7/30/11  Warren and Mike finally had a chance to work on this machine again. We pulled the smoked power supply from the incomplete PDP-8/L and installed in this system. Replacing the power supply is quite a project and involves removing the front panel and a lot of boards.
We noticed that the power supply from the donor system only had one transformer and the failed power supply had two transformers and a toggle swith instead of the keyswitch for poer on. The power supply schematic only shows one transformer, so we are speculating that the failed power supply was substantially modified during its 40 year life.
When we powered on the reassembled system we were rewarded with lights and no smoke. There are some signs of life! After a little experimenting we found that there were some serious problems with the registers. You can see the light pattern after we turned all of the switches off and pushed the Load Address switch. All of the lights should have been off, but many were on. Each of the M220 modules contains 2 bits of the registers. We swapped pairs of the M220 modules around and observed the changes in the light patterns. It looks like only two of the six M220 modules are fully functional. From some quick Googling it looks like the SN7474N chips are a common failure mode for these modules. At least those chips are common and inexpensive.
8/12/11
Ulrich N Fierz of Zurich Switzerland donated two yellow and two orange replacement keys for the front panel.
Mike bought an HP 10526T Logic Pulser, HP 10525T Logic Probe, HP 10528A Logic Clip, and an HP 10529A Logic Comparator. These are the 35 year old tools that are recommended to debug the PDP-8.
Dan found the double-sided Flip-Chip extenders so we can debug the M220 modules in the system.
8/20/11
 Warren and Mike continue debugging the M220 Major Register modules in this system. We started two weeks ago by moving the six M220 modules around in the system and observing the changes in the light patterns. We marked which modules had odd or even or both bit issues. The goal was to get the Memory Address register working because there is no way to Deposit or Examine memory without it.
Some of the Memory Address bits were always on. By observing the lights we could see that some of the Accumulator bits were always on and the corresponding bits in the Memory Address register were always on. The HP 10528A Logic Clip and the HP 10525T Logic Probe were really helpful determining that the AC Enable signal was always on. That was mixing the contents of the Accumulator with the contents of the Switch Register. After chasing the stuck AC Enable signal through the M617 in slot A9 to the M160 module in slot D9 we determined that either the DEC7450 E3 or the DEC7460 chip E4 was defective. There is no way determine which one was defective and we didn't have spare ICs so we swapped the M160 module with one from the parts PDP-8/L. After swapping the M160 the AC Enable signal was working OK. We tested the other two spare M160 modules and those worked OK too. Nice to have some spares! With the AC Enable signal behaving we determined that only one M220 had a problem with the Memory Address register. After a little debugging we found that half of the DEC7474N E4 was defective. We replaced the chip with a "new" TI SN7474N that had a date code only two years newer then the PDP-8/L. The pen in the picture at the left is pointing to the replaced SN7474. After the M220 was repaired we determined that all of the bits in the Memory Address register will load from the Switch register correctly.
After some more experimenting we found that repeated pushes of the newly installed Examine switch do not increment the Memory Address register. If you turn bit 1 of the Switch register on the part of the Memory Buffer is increment. It looks like there is something else wrong with the control logic for the Major Register boards. That will be the project for next week.
We need to get the registers working correctly before we can address any of the other probems with this system.
8/27/11
Old problems:
1. MA does not increment when SR=0, LA, EXAM. 2. MB lower bits seem to increment when SR=1; LA, EXAM,EXAM,EXAM... 2b. Two MB bits (bits 4,5?) seem to toggle together i.e. not increment like the lower bits (0 to 3?) Debugging problem 2: Looking at MB11 (AB02 M220) (Schematic D-BS-8L-0-9 Major Register Gating, Sheet 3, Zone 1 & 2) REG BUS 11 is showing incremented value (wrong). ADD output is also wrong. Looking at AND-OR terms, SR ENABLE is ON (wrong) when EXAM,EXAM... Looking at SR ENABLE (Schematic D-BS-8L-0-4 Reg. Output Gate Control, Zone B4) A08 M617 pin E1 is SR ENABLE. A08 M617 pins A1,B1 (inputs) are wrong. Driven by C12 M115 pin U1. C12 M115 inputs P1,R1,S1 are okay. So, C12 M115 E2 7410 is bad. Swapped in a spare. Works (does not increment). Note: At some point, we determined SR=2 causes MB10 and up to increment. Now, it makes sense. Since SR ENABLE was incorrectly being enabled, it was ADDing the SR to MEM read value, which was being written back to CORE (remember: CORE read is destructive, so it writes back the MB value). So, CORE seems to read and write but always at 0000 (Problem 1: MA does not increment) Problem 2B has changed. The affected bits seem to be stuck on. We tried swapping: Major register bits (AB02 thru AB07 M220s), Sense Amps (A18,A19,A20,B18,B19,B20 G020s). Inhibit Drivers (A23,B23,B24 G228s) Much head scratching...(what's really in memory????) Eventually, we decided all M220s seem okay, but 6 bits are stuck either high or low. Current problems: 1. MA does not increment when SR=0, LA, EXAM, EXAM... 2. 6 memory bits are stuck high or low. New problems noticed: 3. RUN -> RUN light. STOP does not stop, but SINGLE STEP does stop. 4. ION is on (related to problem 1?). 9/10/11 If you do a Load Address and then RUN, the STOP key doesn't work. Pushing SINGLE STEP will stop the processor. Next we looked at the M160 module in slot D09. The E1 pin went high when the STOP key was pressed. high for stop (OK). That is OK. We then moved to the M111 module in slot C07. It is in section D5 on page D-BS-8L-0-3 of the schematics. We found that the F SET-N signal on pin M2 was always high. We moved to the M117 module in slot C11. It is in section C5 on page D-BS-8L-0-3 of the schematics. We looked at the M113 module in slot D12. It is in section B2 on page D-BS-8L-0-3 of the schematics. We traced the SPECIAL CYCLE signal back through pin D2 on the M111 module in slot D13 at section B2 on page D-BS-8L-0-3 of the schematics We looked at the M117 module in slot C11 at section C5 on page D-BS-8L-0-3 of the schematics. We moved to the M115 module in slot C09 at section D4 on page D-BS-8L-0-3 of the schematics. The current behavior is: We probably got confused by the E SET signal behavior because the 5000 JMP and 7000 NOP instructions do not have an Execute cycle. We set the switches to 0000, then LOAD ADDRESS, then DEPOSIT, and continued with the E SET signal. We looked at the M117 module in slot C11 at section C5 on page D-BS-8L-0-3 of the schematics. We continued with the M117 module in slot C11 at section C2 on page D-BS-8L-0-3 of the schematics. We moved to the M216 module in slot B11 at section B2 on page D-BS-8L-0-3 of the schematics. At this point it looks like we fixed a major problem with the BRK SYNC-N signal so that the FETCH and EXECUTE cycles work, but we broke some other behavior with LOAD ADDRESS. Sometimes when we press the LA key the SW register contents are not loaded into the MA register. We will need to back out these module swaps to see if we can determine what we fixed and what we broke. I will fix the broken modules so we can put them back in the machine to see if it behaves better. We assumed, but really don't know if the NOS modules was OK.
10/08/11
During the last debug session we replaced the broken M113 in slot D12. This fixed the floating SPECIAL CYCLE signal and allowed the FETCH/EXECUTE cycles to work, but broke the Load Address switch. We replaced the NOS M216 in slot D12 with another one, but is made no difference in the behavior. We put the NOS M113 back in slot D12 and now LA switch works. Well, at least it worked once. Subsequent operation of the LA switch did not work correctly.
We set the swtches to 0000, operated the LA, DEP, DEP 0000 LA SS START fetches, CONT executes CONT no lights Our guess is that fixing the SPECIAL CYCLE signal unmasked yet another problem in the 8/L. We put the broken M113 slot D12 so we could debug LINK not cleard by START. Looking at LINK not cleared by START. We tried tried storing CMA CML instructions in core and executing them. 0000 LA 7020 (CMA CML) DEP MB is 7020 0000 LA EXAM doesn't read trying to DEP at non 00, it appears that EXAM clears MA and DEP clears MA We put the NOS M113 back in slot D12 and verified that LA is not working. Random MA, START does FETCH/EXECUTE. On the M617 in slot B08 pin M1 is high, pulse low on LA (ok). all switches pulse it except CONT (ok). Set the switches to 0000, did a LA, MB = 4010. On the M220 in slot AB02 looking at enable signals. We saw a pulse on NO SHIFT AE1 (ok), always high PC ENABLE BS2 (bad), pulse on MEM ENABLE BU2 (ok? transfer from mem). On the M617 in slot A08 pin V2 signal PC ENABLE low after power, stays high after EXAM. With V2 high, T2 is always low. On the M113 in slot B13 pin E1 signal F SET is always high after first EXAM, no pulse lo. Pin D1 Signal TS4 is always high after first EXAM, no pulse lo. On the M216 in slot C04 pin V1 low, pulse high on LA, EXAM, DEP. We operated the START switch (running, FETCH and EXECUTE flickering) The signals on pins V1 & V2 are in the wrong state. Pin U2 always low (bad). Pin N1 TP3 pulses (ok). On the M113 in slot C05... START (running, FETCH and execute flickering) Signal TP3 on pin A1 pulses (ok), signal IOT-N on pin B1 always high, pin C1 pulses (ok), pin D1 pulses (ok), pin E1 always low (bad?), pin K1 always low, pin J1 always hi, pin H1 soft high !!! In the M310 in slot D08... Pin F1 soft high, the 7440 (E1) pin 8 is output F1 soft high, pins 9,10,12,13 are low. The M310 in slot D08 is defective. We tagged it for repair and replaced it with NOS part. LA works now! Setting different addresses + LA gives different MB (constant for same address) so it looks like we can read core again. Current issues. EXAM doesn't inc MA, LINK is always on (START should clear LINK), and DEP changes MA. We tried the switch sequence: 0000 LA 6000 We cannot tell if DEP changes memory. At this point we decided to look a the simpler problem of LINK not being cleared on START. It appears that the AC is cleared by START. We looked at the M216 in slot B11 which contains the LINK Flip-Flop. Pin L2 signal clock - START pulses, Pin M2 signal data always high. We looked at the M160 in slot B10 which contains the LINK data logic. Pin R1 output is always low!!! We found that LINK is not always set at POWER on. Signal POWER on with LINK high Pin R1 output high, pin D1 RIGHT SHIFT low, pin F1 DOUBLE RIGHT SHIFT low, pin J1 NO SHIFT high (no pulse on LA,START), pin L1 LEFT SHIFT low, pin N1 DOUBLE LEFT SHFIT LOW, pin V2 ADDER L-n always low (no pulse on LA,START) We looked at the M160 in slot A10. Pin V2 is always low (no pulse on LA,START), pin V1 low, (ok), pin S1 high (ok), pin U1 high (no pulse on LA, START) We looked at the M160 in slot B10 Pin U2 is always high CARRY OUT 0-n. We looked at the M160 in slot A12, pin V2 signal L ENABLE is always low (bad?), Pin U1 OP1 low (ok), pin V1 KEY ST tracked the START key (ok), pin U2 MFTS2 pulsed on START. We replaced M160 in slot A12 with NOS part and now LINK clears at START!!!!!! We tagged the defective M160 for repair. 11/19/11 Current issues. EXAM doesn't inc MA DEP changes MA. Debugging. We decided to look at the issue where EXAM and DEP doesn't increment MA, and MA has the wrong value after operating either switch. To save cycles the PC is written into the MA during T1 and the MA+1 is written into the PC during T2. Bits 4 and 5 of the MA contained a 1 & 0 after EXAM or DEP so we put the M220 from slot AB05 on extender. We put the M617 from slot B8 on an extender and looked at E1 pin 6. It is low. We put the M160 from slot A13 on an extender. E1 pin 8 is floating. We swaped The M160 in slot A13 with the M160 in slot D9. We decided to investigate why the MB was always 60xx. We put M113 in slot C15 on an extender and looked at pins A1: strobed; C1: strobed. We put the M310 in slot D15 on an extender and looked at pin H2: strobes. We put the M617 in slot D17 on an extender and looked at pin S1: strobes once per power up, M1 strobes every time EXAM & DEP are activated. We put the M216 in slot D16 on an extender and looked at pins R2 & P2. They strobe every time EXAM & DEP are activated. We put the M617 in slot D17 on an extender and looked at pins R1 & P1. They strobe every time EXAM & DEP are activated. Pin S1 did not change. We swaped the M216 in slot D16 with card from parts machine....no strobes on pin S1 of the M617 in slot D17. It is amazing how many broken SN7474 chips are in this system 12/03/11 Current issues. Memory is not read or written on EXAM or DEP operation.
Debugging. We looked at the M216 module in slot D16 because that Flipchip contains all of the SN7474 flip-flops that control the memory states. We looked at the M310 module in slot D15. See page D-BS-8L-0-13, section C4 in the schematics. We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics. We looked at the M113 module in slot C15. See page D-BS-8L-0-13, section D2 in the schematics. We looked at the M216 modlue in slot D16. See page D-BS-8L-0-13, section D5 in the schematics. We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics. We pulled the G020 modules in slots A18, A19, A20, B18, B19, and B20 to isolate the problem. We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics. We swapped the M310 modules in slots D14 & D15. See page D-BS-8L-0-13, section C4 & C5 in the schematics. We decided to do a Sanity Test to make sure that the M310 module in slot D15 was causing this problem. 12/09/11 Current issues. Memory is not read or written on EXAM or DEP operation.
Debugging. Since the memory control logic seems to be working correctly now I looked at the eight G221 X and Y memory selectors to see if the MA was getting decoded into core memory selects correctly. I started with the G221 module in slot C23 which decodes the MA00(0), MA01(1), and MA02(1) signals. The G221 module in slot D24 had a defective SN7400 at E3. I replaced all three modules with a good ones from the parts machine. Most of the G221s in the parts machine were also defective, but I found three good boards. 12/22/11 Current issues. Memory is not read or written on EXAM or DEP operation.
Debugging. Looked at pin D1 of the G020 in slot B20 to see if the STROBE FIELD 0 signal was present when the EXAM or DEP key was pressed. It was not. Looked at pin S2 of the M360 in slot C17 to see if the STROBE FIELD 0 signal was generated. It was not. Now I see the SW contents in the MB when the DEP key is pressed. Progress, but the memory still does not work. I looked at the M220 module in slots AB02. I could see different data on pins BR1 and BV2 when EXAM was pressed. I looked at the M617 module in slot A08. See page D-BS-8L-0-4, section D7 in the schematics. The memory looks like it is partially working now. I looked at the G221 module in slot D24. 12/24/11 Current issues. Memory is not read or written on EXAM or DEP operation.
Debugging. I replaced the SN7400 on three broken G221 modules with SN5400 Mil. Spec. chips that Warren donated, so we hopefully have three working ones. I checked all core locations with just one address bit on and found that core locations with the 3, 4, or 5 bit on cannot be written. At this point I think that everything that decodes memory addresses is working correctly and really didn't know what to try next. I toggled a small instruction test program into core at 200 and this time it ran. 12/27/11 Current issues. The AC is not affected by any instructions.
Debugging. Dan and Mike worked on the AC problem today. At this point we decided to see if the bits in the instructions were getting decoded correctly. We looked through the signal list that Vincent Slyngstad gave us with the intention of pulling boards that connected to the OP 1 signal. We tried the M113 in B13, the M160 in A12, and the M115 in A11. We tried a number of little test programs from David Gesswein. None of the instructions that conditionally skip based on the contents of the AC work. 12/29/11 Current issues. Need to test all instructions.
Debugging. We tried the SZA, SNA, SMA, SPA, CML, SNL, SZL, SKP, OSR, CLA & CLL, and they all work. The CLA and CLN instructions clear both the AC and the Link at the same time. ISZ clears the AC and writes the MA into core pointed to by the MA. DCA has 0 in the MB during the E phase so I don't think that it is writing to core. 12/31/11 Current issues. Need to test all instructions.
Debugging. We tried the CLL instruction again. It clears both the AC and the Link. That is not OK. The AND instruction didn't work. 1/2/12 Current issues. Look at the memory reverence instructions to find out why they don't put the address in the MA.
Debugging. I tried to write to 7777 with the MEM PROT switch on. The PROT light lit and it did not write to core. Perfect! I looked at the M220 in slot AB04, D-BS-8L-0-9, section A8 in the schematics. I decided to see if TS4 and TP4 are working. I looked at the M117 in slot C13, D-BS-8L-0-4, section C5 in the schematics. I tried all of the toggle-in test programs from David Gesswein. I put the M707 in slot CD31 on the extender. I put the M115 in slot D04 on the extender. I made a cable to go from the AMP connector on the W076 in slot D33 to the AMP connector on a VT220. I tried a TTY echo program, but the program looped on the KSF instruction. 1/14/12 The system has worked OK the last two Saturdays we turned it on. Looks like it might me fixed. Warren tried his home-build RS232 to current-loop converter. At low speeds the laptop to 8/L interface is working OK. 1/28/12 We powered up the 8/L so that we could try Warren's RS-232 to Current-Loop adapter. The program that we left in the system was: We decided to start at the beginning and see if timing states were working. We put the M216 in slot C04 on the extender. We put the M113 in slot C05 on the extender. We ran the test program and were able to echo characters from Warren's laptop through the 8/L. We toggled in the RIM loader, ran it, and sent the BIN loader (DEC-08-LBAA-D) to the 8/L from Warren's laptop. We saw more satisfying blinky lights, and it halted with LINK set and AC=0. That indicates a good checksum! Time to leave. Starting to pack up...
Mike tells Warren to run the diag: "Don't leave me hanging!" Found test document for rev C "MAINDEC-08-D1AC-D.pdf". The operating procedure is; LOAD ADDRESS 0014, START, program halts at 0042.
Then LOAD ADDRESS 0001, START, the program should loop. The program halted at 0055. it's the error halt. So, it looks like the might still be some memory problems. We need to look at memory locations 0011, 0012, 0007, and 0010 to determine where the memory error was seen and what the bits were. We will save this for next weekend. 2/4/12 Today the 8/L was the test bed for the modules in the 8/I. 2/11/12 We continued using the 8/L as the test bed for the modules in the 8/I. 2/28/12 Last Thursday was the one year anniversary of starting on the 8/L project. 5/19/12 We used Warren's 20 mA current-loop to RS-232 converter to load some diagnostic programs into the 8/L. 6/2/12 We loaded the first instruction diagnostic maindec-08-d01c-pb.bin. It failed miserably. We loaded the maindec-08-d1b1-pm.bin Memory Address test. We swapped G221 memory selectors, but it did not move the address of the failure. After doing some more research we found that the 1N4148 is not a suitable replacement for the D672 diodes on the core. We tried the core stack from the PDP-8/I which originally came from the parts PDP-8/L.| 6/9/12 With a lot of help from the usual PDP-8 experts we narrowed the selection of possible replacement diodes to the ones listed in the table below.
I replaced the 1N4148 diodes that I had previously replaced with FDH333 diodes. Unfortunately this did not fix the problem with memory in the 20xx range.
Page 20 of the schematics (DEC-8L-HR2A-D_8Lschem_Feb70.pdf) shows the X-Axis Selection.
That led us back to the diodes on the core stack. We decided to look at the core current wave forms to how the 20xx range compared to the rest of the core. So, now we are back to the diodes on core stack. We setup a power supply with the voltage limit set to 6V, and the current limited to 200mA. We went looking at the eight possible bad diodes by measuring the voltage drop across the diodes. We loaded the RIM loader and tried to load the maindec-08-d1b1-pm.bin Memory Address test. We loaded the RIM loader and tried to load the maindec-08-d1b1-pm.bin Memory Address test. We loaded the RIM loader and loaded the maindec-08-d1b1-pm.bin Memory Address test. During the week we need to find out how this diag is supposed to be run and try it again next week. If this system passed diags, then we can again use it to test the modules from the PDP-8/I and fix the processor in that system. 6/16/12 We loaded and ran the maindec-08-d1b1-pm.bin Memory Address test. We tried a two instruction program; JMP .+1, JMP .-1, to see if the memory contents would not change. We looked at the read & rewrite memory current going through the resistor R1 on the G624 module in slot B25. We though about what modules are connected to the MA, and specifically bit 8. Out of desperation we swapped the G221s for the X-axis, and found that replacing the one in slot D19 fixed the problem. Rerunning maindec-08-d1b1-pm.bin Memory Address test still didn't give us the expected results, so we decided to test instructions. So now we have a catch-22 situation. 6/23/12 We loaded MAINDEC-8I-d01c Instruction Test 1, and single stepped through the tests. We swapped the G221 modules at C23 and C24, but there was no change in the behavior. We tried just running Instruction Test 1 at full speed, but it halted at 0501. We did some more experimenting and found that any instruction at xx00 was replaced with zeros if the program was run at full speed. We spent the rest of the afternoon swapping all of the G221s, G228s, and G224s. At this point we really don't know what is causing this memory behavior. 6/30/12 We decided to swap all of the modules that have anything to do with memory timing to see if We found out right away that bit 6 was not working for all memory locations. We swapped the M216 in D16 & C04, the M113 in C02 & D12, the M115 in D04, the M310 in D06 & D07, We measured the memory voltage on the G624 module in B25. It was 22.98 with the processor running and 23.29 halted. We measured the delay on the M360 module in C17. It was set to 148ns. We decided to measure the delays in the Memory Control logic. The time from the current pulse to the data in the test point on the sense amplifier changes about 100ns between running and halted. Maybe this has something to do with the diode replacements that we made on the core stack?  Click on the image for a larger view.
This shows the "MEM START" signal at the top and the test output Pin E1 of the Sense Amplifier at the bottom.
The delay is 316ns when the processor was running.  Click on the image for a larger view.
This shows the "MEM START" signal at the top and the test output Pin E1 of the Sense Amplifier at the bottom.
You can see that the "1" at the bottom right is shifted to the left about 100ns when the processor was halted.
7/5/12 We continued work in the core memory problems. The 8/L maintenance manual includes a Memory Alignment procedure.  This image shows the STROBE FIELD 0 signal at the top and the "1" data from the test pin E1 on a sense amp at the bottom. One waveform is with the processor in single-step and one waveform is superimposed from the processor running. You can see the large shift in the delay from strobe to data. We think that this is from the FDH333 diodes that we used for repair. Of course when I tried to load the Memory Address Test I found that serial connection between the laptop and the 8/L 7/7/12 We fixed Warren's current to RS232 converter so we could load programs. It seems that the unregulated -30V from the G785board was more like -40V. This is wired to the W076 module and was a little tough on the 40V rated transistor connected to
the current loop. Warren added a resistor across the 20mA connections to reduce the voltage and it works fine now.
We toggled in the RIM loader, and loaded the BIN loader. Unfortunately BIN loader would not run. We fixed a few corrupt instructions and tried to load a diag. The AC was not zeros at the end, so we knew that there were more problems. We loaded the D1B1 Memory Address Test (low) (RIM format). It displayed all kinds of errors in the x6xx and x7xx range. We replaced the G221 in slot D19 with a repaired but not tested one, but it had worse problems. We tried another, and then another and finally got one that worked OK. Now the diag runs fine and displays an "11" every 29 seconds. We also tried the D1B2 Memory Address Test (high) and
that also worked OK.
Now the BIN loader loaded and worked fine. We loaded the 8I-D01C Instruction Test 1 which of course failed instantly. The failure pointed to the the M220 in AB05. We swapped it with a repaired but not tested module and it failed in a different way. We swapped it with another
repaired but not tested module, and another and finally borrowed one from the 8I. Now it will run the instruction diag without problems.
So, at this point the system is looking pretty solid. Next week we will run more diags to prove that it is really running OK. This week I will replaced the FDH333 diodes on the misbehaving core stack with 1N4149 diodes and see if the single-step/running delay in the core stack is gone. If so, we can put the borrowed core stack back in the 8I and go back to debugging that system. 7/14/12
We ran maindec-08-D02B PDP-8 Instruction Test Part 2B. Both the TAD and rotate sections run without errors.
We ran maindec-8I-D02B PDP-8I Instruction Test Part 2B. The SZA test at 0232 failed.
We ran maindec-08-D04B PDP-8 Random JMP Test. It periodically prints "04" and runs without errors.
We ran maindec-08-D05B PDP-8 Random JMP-JMS Test. It periodically prints "05" and runs without errors.
We ran maindec-08-D07B PDP-8 Random ISZ Test. It periodically prints "07" and ran for a few minutes without errors. We set SW9=1.
After running for a while we got an spurious interrupt and the diag halted.
We connected 'scope probes to pin P2 and M2 of the M516 module in slot A33 so we could see if there was a TTY interrupt when there should not be.
It ran for more than an hour in this configuration without a problem. We also tried the diag with SW9=0 and it still runs OK.
We ran maindec-08-D1L1 Basic Memory Checkerboard (Low). We ran it for about 10 minutes and didn't see an error.
Running the memory checkerboard without errors is a really good test of the system and the core.
We ran maindec-8I-D01C Instruction Test 1. It rings the bell about twice/second and runs OK.
We ran Warren's pt_info program against the two images if the maindec-8I-D02B that I had. Both showed errors in the paper tape image.
We loaded in an image that Warren made. It halted at 2433 because location 2430 contained the wrong instruction.
We fixed location 2432 and it halted at 3336. This time we fixed an instruction at 3333.
Now it halted at 3321. Fixing the instruction at 3303 fixed it, and we let it run for several minutes.
Now that we thought that the processor was working well, we put the original core memory stack back in. We ran the maindec-08-D1B1 Memory Address Test for several minutes without an error. It periodically prints "11".
So, now we know that the 1N4149 diodes are OK for a core memory repair.
We ran maindec-08-D1L1 Basic Memory Checkerboard (Low) for about 30 minutes and didn't see an error.
Next week we should run the memory alignment procedure to adjust the memory voltage and the timing. We put the borrowed core stack back in the 8I so we can get back to debugging that system.
7/20/12
We ran maindec-08-D1L1 Basic Memory Checkerboard (Low) for about 10 minutes and didn't see an error.
I guess that means that the processor and memory are still working.
We ran maindec-8I-D01C PDP-8 Instruction Test Part 1. Everything worked OK.
We installed a repaired M220 Major Registers module in slot AB07, this is for bits 0 & 1.
It would not run at all. On inspection of the M220 We found that I installed SN7453 E12 backwards when it was replaced.
I will fix that this week.
We installed another repaired M220 Major Registers module in slot AB07.
We ran maindec-8I-D01C PDP-8 Instruction Test Part 1. It halted at 1466 indicating a problem with the RTR instructions. 7/21/12
We ran MAINDEC-08-D1B1 Memory address test (low) to make sure that everything was still working OK. It was. We swapped the G221 in slot C24 with several repaired modules. Some of them worked OK and will be spared.
Others need more debugging and repair. This time we found defective transistors.
We tried all of the G221 modules from the PDP-8/I and found that one was broken. It was replaced with a spare.
I will repair the broken one this week.
We tested almost all of the spare and repaired module; first in Warren's tester and the in the 8/L.
We are starting to build a good collection of tested and working spares.
7/28/12
We ran MAINDEC-08-D1B1 Memory address test (low) to make sure that everything was still working OK. It was. We tested the two repaired M220 modules by running Instruction Test 1 & 2.
Both worked OK.
8/4/12
MAINDEC-08-D1B1 Memory address test (low) was left in the core from last week, so we ran it just to make sure that
the processor was still working OK. It was!
We loaded and ran MAINDEC-08-D1L1 Basic Memory Checkerboard (Low).
We performed the "memory alignment procedure" while the checkerboard was running and made some adjustments to the memory timing.
We looked at the relationship of the "Strobe Field 0" signal and the ones from the sense amplifiers and increased the delay in the M360 module
so the relationship looked like Figure 5-6 in the Maintenance manual.
We ran the MAINDEC-08-D1L2 Basic Memory Checkerboard (High) for about six hours and checked the timing on all bits. They all look OK.
We even loaded the Focal language interpreter. That worked OK too.
8/13/12
I loaded MAINDEC-08-D1B1 Memory address test (low) to make sure that the processor was still working OK. It was!
I loaded MAINDEC-08-D1L1 Basic Memory Checkerboard (Low) which also ran OK. I used the system to test repaired M220, G020, and G221 modules. They all worked OK and were put in the spares cabinet.
8/18/12
We loaded MAINDEC-08-D1B1 Memory address test (low) to make sure that the processor was still working OK. We tested all of the G221 modules from the PDP-8/I and found two that misbehaved.
9/1/12
We loaded MAINDEC-8I-D02B PDP-8I Instruction Test Part 2B and tested the M707 from the 8/I and the repaired M707. Both worked perfectly for 10 minute diag runs.
We replaced the M216 in slot B11 with the M216 from slot E33 in the 8/I.
The Instruction Test Part 2B diag ran for 25 minutes without a problem, so this is not the misbehaving module in the 8/I.
9/8/12
We loaded MAINDEC-08-D07B PDP-8 Random ISZ Test, and ran for 60 minutes without an error.
We installed the M220 modules from the 8/I and they worked perfectly for a 20 minute diag run. So, we have eliminated the M220 modules from the ISZ diag problem in the 8/I.
11/18/12
The the PDP-8/L came home for the holidays so I could debug the FPGA based paper tape reader emulator. Just to make sure that everything was working OK I ran:
Things to look at during the next debug session. Run the memory alignment procedure to adjust the memory voltage and the timing.
Test the modules in the PDP-8/I using Warren's module tester and the 8/L.
Survey the KSR-33 Teletypes and see if one is close to working. Connect the KSR-33 to the PDP-8/L, load and run diagnostic tests from paper tape.
Diagnostic Passed:
MAINDEC-08-D1B1 Memory address test (low) MAINDEC-08-D1B2 Memory address test (high) MAINDEC-8I-D01C Instruction Test Part 1 MAINDEC-08-D02B PDP-8 Instruction Test Part 2B
MAINDEC-8I-D02B PDP-8I Instruction Test Part 2B
MAINDEC-08-D04B PDP-8 Random JMP Test
MAINDEC-08-D05B PDP-8 Random JMP-JMS Test
MAINDEC-08-D07B PDP-8 Random ISZ Test MAINDEC-08-D1L1 Basic Memory Checkerboard (Low) MAINDEC-08-D1L2 Basic Memory Checkerboard (High)
The boards replaced so far are:
G221 in slot C23.G221 in slot D24. M113 in slot D12. M115 in slot A11. M115 in slot C09. M115 in slot C12. M115 in slot D04. M117 in slot C13. M160 in slot A10. M160 in slot A12. M160 in slot D9.
M216 in slot B11. M220 in slot AB0x repaired. M220 in slot AB05 replaced with a module borrowed from the PDP-8/I.
G020 in slot B18.
G221 in slot D18. G221 in slot D19 repaired. Replaced again with a repaired module. Replaced again with a repaired module. G221 in slot D24 repaired. G228 in slot C25. M310 in slot D07. M310 in slot D08. M310 in slot D15. M360 in slot C17. M706 in slot CD32. M707 in slot CD31. |
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PDP-8/L_Restoration |