DEC PDP-8
2024 Restoration

22-May-24

We did some more investigating this afternoon. Doug reminded us that there are early and late versions of the PDP-8 Maintenance Manual, and there are some design changes in the later version. Since this is S/N 13 it is probably a very early version.

There are a bunch of empty slots on the Memory side of the chassis because the #183 Memory Extension Control and #188 Memory Parity options are not installed.

The FlipChips in slots: 

MA30 through MA25 match the F-87 manual.

MB31 through MB25 match the F-87 manual.

MC31 through MC06 match the F-87 manual except that it has a B684 Two Bus Drivers FlipChip in slot MC19 instead of a B602.

MD30 through MD06 match the F-87 manual except that it has G203B Memory Selectors instead of G209. It looks like a G209 is an upgraded replacement for a G203.

ME28 through ME14 match the F-87 manual.

MF28 through MF15 match the F-87 manual.

24-May-24

The empty slots in the Processor side of the chassis are for the #189 A-D Converter, KR01 Power Interrupt, and #681 Data Line Interface options that are not installed.

The FlipChips in slots PA36 through PA01 match the F-87 manual, except that there is an S111 Diode Gate in slots PA22, PA24, PA25, PA27, PA30, and PA31 instead of a lower power R111, and an R302 Delay in slot PA36 instead of a W501 Schmitt Trigger.

The FlipChips in slots PB35 through PB01 match the F-87 manual, except that they are High-Power S versions of the FlipChips in slots PB19 through PB34 instead of the lower power R FlipChips. Slot PB36 holds an R602 Pulse Amplifier instead of an R405 Crystal Clock. The R405 was moved to slot MF29.
The FlipChips in slots PC36 through PC01 match the F-87 manual, except that many of the Lower-Power R versions have been replaced with High-Power S versions.
The FlipChips in slots PD36 through PD01 match the F-87 manual, except that many of the Lower-Power R versions have been replaced with High-Power S versions.
The FlipChips in slots PE36 through PE01 match the F-87 manual, except that many of the Lower-Power R versions have been replaced with High-Power S versions.
The FlipChips in slots PF36 through PF01 match the F-87 manual, except that many of the Lower-Power R versions have been replaced with High-Power S versions.

25-May-24

We removed all 12 front panel switches that had broken pivots. We need to 3D print a drilling fixture, drill out the broken pivots, and replace the pivots with 1/16" or 0.0625" acrylic rod. We reassembled the front panel with the good switches in the far right positions.

We took better pictures of the Processor clock modifications. We need to reverse engineer this clock circuit.

29-May-24

We disconnected the power harness connecting the backplanes to the power supply and removed the power supply. That will allow for a closer inspection for damaged components. allow better access so we can reform the capacitors, and make it easier to test.

3-Jul-24

We spent 2.5 hours fiddling with the switch paddle for bit-3 and never got it to fit correctly and have the pivot pin go into the holes in the metal brackets in the switch. We drilled the holes in the metal brackets to 0.070", but that didn't help. We noticed that the 0.062 acrylic rod diameter varies from 0.062 to .070 along the length, so we selected parts of the rod with a smaller diameter. We have no idea what the problem is at this point.

10-Jul-24

We continued work on the front panel switch pivots. We measured the diameter of the Acrylic rod, and used parts that were close to 0.062" diameter. The new switch that I was using for a test fit has smaller metal brackets, so the real switches need more clearance around the plastic paddles. With some more plastic carving on the switch paddle we easily installed the next switch. We got 4x switches done, so only 4x switches to go. 

24-Jul-24

We have just five switches left to do. Between visitors we managed to get two more switches fixed. Hopefully Saturday we will finish the switches and get back to debugging the system.

27-Jul-24

All of the front panel switched are now repaired!

We measured the resistance of all of the bulbs. All have continuity except for the six bulbs for the memory address extension and the unused bulb for the instruction decoding. There are some differences in the resistance readings, so there may be some differences in the lamp brightness.

Pressing LOAD ADDR will load all of the address switches into the PROGRAM COUNTER.

Pressing the EXAM switch loads the PROGRAM COUNTER into the MEMORY ADDRESS and turns some of the lights on in the MEMORY BUFFER, increments the PROGRAM COUNTER, and lights the TAD and EXECUTE lights. The contents of memory displayed by EXAM is repeatable.

Pressing the DEP switch loads the PROGRAM COUNTER into the MEMORY ADDRESS and loads the switches into the MEMORY BUFFER, increments the PROGRAM COUNTER, and lights the DCA and EXECUTE lights. The contents of memory does not change.

Pressing STOP does not stop the processor when it is running. Fixing this is the project for Wednesday.

The instruction decoding lights work.

2-Aug-24

We decided to fix the STOP switch today. The SING STEP switch work OKs, and the wiring for those switches goes to the same circuitry, so it should not be difficult to fix. It turned out to be easier to fix than we anticipated. While we were fiddling with the STOP switch it started working. We declared it fixed and moved to the next problem.

Time to look at the SING INST switch. We looked at pin PB5-R for the SINGLE INST. signal. The signal is normally low, and goes to ground when the switch is activated, so it is OK. We looked at pin PB30-R for the /SINGLE INST. signal. It is normally ground and goes low when the switch is activated, so it is OK. We looked at pin PB32-H for the junction of lots of the switch signals. It is normally low (-3.0V) and goes to -1.0V when SING STEP is activated and to -1.5V when STOP is activated. If both the SING STEP and STOP switches are activated the signal goes to -0.5V. Pressing the EXAM or DEP switch drives the signal to -0.2V. We swapped the S111 flipchips between slots PB32 and PB31. Now the signal goes to -1.0V when the SING INST. switch is activated, which looks OK. Most likely transistor Q1 on the S111 from slot PB32 has low conductivity. We replaced Q1, a DEC3639, on the S111 in slot PB32, and now there is no activity on PB32-H when the SING INST. switch is activated. Maybe a bad new transistor or maybe the emitter and collector pins are in different positions on the transistor? The diode drops base-emitter and base-collector on the original transistor measures about 1.0V and 0.0V, so the original transistor looks like it doesn't have a catastrophic failure.

We will continue debugging this on Saturday.

3-Aug-24

We tested the Fairchild DEC3639B transistor that we removed from the S111 FlipChip. It tested OK in a DVM and had a beta of 27 so it is probably OK. I tested some of the replacement Fairchild 2N3639 transistors that I bought on eBay. Most had a beta around 7 with one 10, one 14, one 18, and one at 45. We tested NOS DEC 3639B transistors from a DEC field service tool kit. They had a beta of 32, 44, 84, 110, 124, 142, 156, 175, and 177. The datasheet says that the beta or hFE should be at least 30 and a maximum of 120. so only the replacement that I bought on eBay with a beta of 45 meets the datasheet requirements. We didn't get far with debugging because we had lots of visitors at the museum.

11-Aug-24

We received the special Acrylic adhesive and the 1/2"x1/2"x6" pieces of Acrylic that we will use to reinforce the corner joints in the Acrylic.

We looked at the RUN STOP signal, and why the STOP switch would not activate that signal. KEY STOP would bring the signal up to -2V and SINGLE STEP would bring it to -1V. We checked the shared ground on the front panel switches, an there was no difference between these two signals. We pulled each FlipChip connected to pin E of the S107 in slot PB33 one at a time to see if the behavior of the KEY STOP and SINGLE STEP signals changed. When we pulled the S107 inverter in slot BD31 the KEY STOP and SINGLE STEP signals went to ground when the signal was activated. We replaced D1, a D-662 diode on the S107 in slot PD31, and now the KEY STOP and SINGLE STEP signals work OK.

We looked at the behavior of the DEP and EXAM switches. EXAM shows repeatable data, but we can't change it with a DEP. That will be the next thing to fix.

14-Aug-24

We noticed that the MEMORY ADDRESS bit-3 is always on. That should be easy to diagnose and fix in the limited amount of time available today. We swapped the R211 FlipChips in slots PC10 & PC11 for bits 3 & 4. Now bit-4 is always on, so the problem is on the R211 FlipChip now in slot PC11. We put the R211 FlipChip from slot PC10 back in slot PC11 from where it came. We tested all of the diodes on the R211 that are part of the MA circuitry. One D-664 diode measured 0.103mV drop in one direction and 0.209mV in the other. It should measure 0.7mV and 0.0mV. We replaced it with a new D-664 (1N3606) and now all of the bits in the MA work OK.

17-Aug-24

Now for the DEP key. Addresses below 0040 and ending in 0, 1, 2, or 3 contain all zeros. Addresses below 0040 and ending in 4, 5, 6, or 7 contain some random non-repeatable bits. All addresses above 0040 contain random bits. My guess is that we have some addressing issues for the low addresses in memory. We can't deposit anything to any address, so there are some other memory issues too.

We looked at page 2-4 in the F-87 Maintenance manual to see how the DEP key works.

During:

• SP0 the RUN flip-flop clears

• SP1 the AC, MB, and IR clear, PC -> MA, PC+1

• SP2 a DCA instruction -> IR, SR -> AC, the MEM START signal goes active

• SP3 1 -> RUN flip-flop, @ T1 0 -> RUN flip-flop, so it executes only one DCA instruction

• The memory strobe signal is disabled so MB stays = 0, @ T1 AC -> MB, 0 -> AC

• T2 the 0 in the RUN flip-flop inhibits the T2B pulse

We looked at pin T on the S603 in slot PB36. The signal goes high for about 700nS when the START, EXAM, or DEP switches are activated.

It looks like this part of the processor is OK. Time to look at core memory.

We looked at the (0) and (1) outputs of the MA register at the G209 Memory Selector FlipChips. All of the bits look OK.

There seems to be a non-deterministic problem with the READ & WRITE signals. Sometime when EXAM is activated we see a read signal and then both READ and WRITE signals. Sometimes just a READ and then a WRITE.

We looked at the MEMORY START signal along with READ & WRITE. When we get concurrent READ & WRITE signal we also see a second MEMORY START signal.

We looked at the SP2 signal, and never see an extra SP2 when we see an extra READ signal.

We looked at the T2B signal along with MEMORY START, READ & WRITE. Periodically we see glitches on the T2B signal at the edges of the WRITE signal that are large enough to trigger the MEM START signal.

The INH voltage is 29.8VDC, and the R/W voltage is 46.4VDC. 

21-Aug-24

We looked at the MEM ENABLE(1), READ(1), INHIBIT(1), and WRITE(1) signals from the R204 Flip-Flop in slot MD16. MEM ENABLE(1) is active for 3.5uS, READ(1) starts coincident with MEM ENABLE(1) and is active for 700nS, 2.25uS after WRITE(1) goes inactive INHIBIT(1) goes active for 500ns, and 75ns after INHIBIT(1) goes active WRITE(1) goes active and goes inactive 400ns later. All of these signals look OK this week. Pressing DEP or EXAM yields a 3.5uS memory cycle. When RUN is presses the first memory cycle is 3.5uS and the rest are 1.2uS.

 We looked at MEMORY START and MEM STROBE. The MEM STROBE pulse starts 300nS after MEMORY START.

We looked at the READ and WRITE signals relative to MEM START. We could not find the R650 in slot MC16 as shown in the schematic, so we looked at the READ and WRITE signals on the input to the G209 in slot MC12. The signals have the same duration and timing as the READ(1) and WRITE(1) signals.

We looked at INHIBIT(1) and MB0(0) on the G209 Inhibit Driver in slot MC21. The INHIBIT(1) pulse looks OK and MD0(0) is at -3V when the switch is off. The + and - output voltage changes if switch 0 is on and off.

We looked at MEMORY STROBE (MEM STROBE) and SA0 on the G007 Sense Amplifier in slot MA25. The SA0 output goes to ground for 100ns after the MEM STROBE starts when there is a 1 in memory bit 0.thermister 

28-Aug-24

We read through the mem-tune-b.pdf file from www.pdp8online.com.  It suggested that we remove the B360 FlipChip in slot MD20. This FlipChip implements the MEMORY STROBE delay, and when removed prevents the contents of memory from being transferred to the Memory Buffer register. We ran the processor and it happily executed AND instructions as if all of the memory was zeros. As expected the AND, FETCH, EXECUTE, and RUN indicators on the front panel were lit.

31-Aug-24

We were pulled the G808 Power Supply Control for the INHIBIT and READ/WRITE power supplies. All of the diodes and transistors on both boards had reasonable voltage drops. The R/W thermistor had a resistance of 315 Ohms and the INH thermistor had a resistance of 452 Ohms at room temperature. The G808 schematic says that the resistance should be 330 Ohms at 25C. The INHIBIT G808 is in the slot towards the outside of the chassis, the READ/WRITE G808 is towards the inside. The G808s are marked on the handles INH and R/W. The INHIBIT supply is making 29.9V and the READ/WRITE supply is making 46.3V. Adjusting the potentiometer on the R/W G808 FlipChip does not change the output voltage. Adjusting the potentiometer on the INH G808 FlipChip does change the output voltage. We swapped the positions of the two G808 Flipchips. Now the INHIBIT supply is making 32.2V and the READ/WRITE supply is making 46.6V. That means that the regulation problem is not on the G808 FlipChips.

The schematic says that there is a 2N3715 60V @ 10A pass transistor that regulates the 40V from the power supply based on the control signal from the G808 FlipChip. There are actually two 2N3236 transistors on the heat sink which are 90V @ 15A transistors. Maybe someone substituted the original transistors with ones with a higher capacity, or DEC decided to use lower capacity, lower cost parts on later machines.

4-Sep-24

We pulled both of the 2N3236 pass transistors and measured Base-Collector and Base-Emitter voltage drops with a DVM. Both measured about 0.6mV with the red lead on the base and zero with the black lead on the base. They are probably OK so we reinstalled them.

The upper Inhibit transistor has a 16.5V drop across the Collector-Emitter and 15.9V Collector-Base.

There is 16.6V between the upper Inhibit transistor's Collector and DC Ground, so this one is regulating. There is 346mV between the lower R/W transistor's Collector and DC Ground, so this one is not regulating. The lower transistor is on saturation and is fully turned on.

The voltage on the Base of the Inhibit transistor is 570mV with the processor stopped and 790mV with the processor running. The voltage on the Base of the R/W transistor is 370mV with the processor stopped and 400mV with the processor running. Adjusting the trimpot on the R/W G808 FlipChip does not change the voltage on the Base of the R/W pass transistor.

7-Sep-24

We swapped the Inhibit and R/W NTCs to see if the R/W NTC is causing the problem with regulation. The R/W voltage is 46V with the processor stopped and 43V when running. The Inhibit voltage is 30.3V with the processor stopped and 28.8V when running. It looks like the different resistance in the two NTCs is nor causing the problem.

Dave G. said that with the Base voltages on the pass transistors as they are they should both be regulating. He suggested swapping the pass transistors to see if the fault stays with the R/W supply or moves to the Inhibit supply. We swapped the Inhibit and R/W pass transistors. The R/W voltage is 46V with the processor stopped and 43V when running. The Inhibit voltage is 29.7V with the processor stopped and 29.4V when running. It looks like both transistors are capable of regulating.

One side of R11 on the G808s is connected to +10V. On the Inhibit G808 the other side of R11 has 0.9V, so Q4 is partially conducting. On the R/W G808 the other side of R11 has 0V, so Q4 is fully on. Having the base of Q5 on the Inhibit supply at 0.9V should make Q5 partially conduct and turn Q1 pass transistor partially on, and regulate the supply. Having the base of Q5 on the R/W supply at ground should make Q5 turn off and turn Q2 pass transistor off, and make no voltage from supply.

The Q5 Emitter on the Inhibit supply that connects to the base of Q1 the pass transistor measures 0.52V so Q1 isn't conducting much. The Q5 Emitter on the R/W supply that connects to the base of Q2 the pass transistor measures 0.06V so Q2 shouldn't be conducting much. 

I removed the pass transistor Q2 for the R/W supply. Now the voltage on the base of Q2 is 10.5V because the G808 is trying to increase the current through the R/W supply.

Note: The right G808 is for Inhibit and the left G808 is for R/W. The upper pass transistor, Q1, is for the Inhibit supply, and the lower pass transistor, Q2, is for the R/W supply. 

11-Sep-24

We have a new volunteer, Grant, who seems to know a lot about the physics of semiconductors. We reviewed the R/W power supply debugging that we have done so far. He agreed that the pass transistor Q2 was the most likely problem. We pulled it, and measured the base-collector and base-emitter voltage drop. Both were about 0.6V and 0V with the leads reversed, so the transistor looked OK. Grant suggested that we check the resistance collector-emitter. We were a little surprised to find it was shorted. We set Q2 down and checked Q1 for the Inhibit power supply. Q1 was OK, including the emitter-collector resistance. We rechecked Q2 and it was OK. With the DVM leads on the collector and emitter we shook Q2 and could see the emitter-collector short was intermittent. There is something conductive floating in the Q2 case.

We replaced the larger than necessary 2N3236 with a correct NOS 2N3715 from a DEC field service kit. The R/W supply now made 17V, so at least it is regulating. We adjusted the trimpot on the R/W G808 and could only get the supply up to about 22V, so there is still a problem.

14-Sep-24

Grant wants to cut open the failed 2N3236 to see if we can find the conductive part that is floating around inside.

We measured the voltage on the Inhibit power supply at 28.9VDC.

We measured the voltage on the R/W power supply and were surprised to see it at 32VDC instead of the 22VDC we saw last week. We adjusted the trimpot to make the the output 27.2VDC. We need to adjust both to set the Inhibit and R/W current in the core memory.

We started looking at the behavior of the core memory now that the Inhibit and R/W power supplies are probably regulating OK. We deposited 5252 to sequential addresses. We examined addresses sequentially starting at 0000. Addresses ending in 0, 1, 2, or 3 show nothing in memory. Addresses ending in 4, 5, 6, or 7 show partially the 5252 memory pattern.

We noticed that the schematic calls for G209 Memory Selector, but this system has G203 Memory Selectors from a PDP-5. We also noticed that there are 7x G603A flipchips in the memory and 8x sockets. The G603A in the front socket is missing 3x of the baluns. We replaced the missing G603 and the damaged G603 with NOS spares. The memory behavior didn't change.

We were able to toggle in a JMP to 0005 and a JMP to 0004 in memory locations 0004 and 0005. We set the SING INST switch, did a LOAD ADDR of 0004, and pressed START. It executed a JMP instruction to 0005. We pressed CONT and it executed a JMP 0004. We turned SING INST off and pressed CONT. It continuously ran the JMP-JMP instruction pair.

We looked through the Memory Tuning manual to adjust the Inhibit current. The Ferroxcube sticker says 305mA for Inhibit and 300mA for R/W. The Inhibit current was about 50mA low, so we adjusted the Inhibit power supply voltage. At 33.5V the Inhibit current was 305mA. We adjusted the R/W current to 300mA ad the resulting R/W power supply voltage was 32.1V.

After adjusting the Inhibit and R/W current the memory is working OK.

We noticed that the PC doesn't change when we single-step the processor. It does work correctly. Well not all the time.

The deposit part of DCA is depositing random information.

18-Sep-24

We did some more instruction testing using the toggle-in programs. Results are in the table below.

21-Sep-24

We need to fix the DCA instruction, make a Teletype console cable, and see if the serial console works. Grant tested the DCA instruction with a range of addresses, and it seems to be working today. Maybe there is a thermal issue?

Grant and Cully looked at LOTS of memory addresses and found a few that misbehaved. Address 7777 is a problem, and we need that to work for the starting address for the BIN Loader.

It looks like the G203 Memory Selector is 1/2 of the newer double-wide G209 Memory Selector used on a newer PDP-8. The system schematic for the memory matches the machine we have, but the G203 design is different from 1/2 of the G209. We will need to reverse engineer the G203 so we have a schematic for repairs.

We looked at the MA register inputs to the G203 FlipChips. The MA11(0), MA11(1), MA10(0), MA10(1), MA9(0), and MA(1) signals to the G203 FlipChips all correctly represent the contents of the MA register. We will need to look at the other six addresses to see if they also work OK.

There are lots of adjustments in the memory circuitry that we will need to perform to make sure that everything is working correctly.

We found a W070 FlipChip with some console cable attached. We need to install a 6-pin Molex connector on the end so we can connect it to the VT220, ASR33 Teletypes, and PCs. That will let us load diagnostic programs from paper tape images. 

25-Sep-24

We tried to load the RIM loader in locations 7756-7775. All worked except locations 7774-7777. This may be a problem with diodes on the G603 FlipChips plugged into the front of the core memory box. We swapped the first and last G603 FlipChips, and now locations 7774-7777 work. The G603 from slot MP8 had a broken transformer, so we replaced it with a spare. We loaded and ran the RIM loader. Since there is nothing connected to the console port it is just loading garbage. The next project will be adding a Molex to the cable and connecting it to an ASR33 Teletype.

2-Oct-24

Grant wrote an instruction test sequence and used it to test the remaining instructions. The updated instruction test results are in the chart below. We still need to test the EAE instructions, but that might be easier running a Maindec.

We needed to attach an 8-pin Molex connector onto the end of the console cable. We couldn't find our documentation on the pinout of the connector so we reverse engineered the console cable from the PDP-8/I. The Molex connector plugs directly onto the back of a VT220 terminal. We installed a pigtail with the matching connector on the Teletypes that we use for PDP consoles, and for the Altair console. That lets us switch terminals between machines. We also have a signal-powered RS-232/20mA Current-Loop converter that Warren Stearns made that we use to connect a laptop to any of the PDPs and the Altair. 

W070 FlipChip Wire Color Molex Pin Function

4 Red 5 Transmit+

6 White/Yellow 3 Receive-

Relay- Blue 4 Reader Run-

3 White/Gray 2 Transmit-

7 Black 7 Receive+

Relay+ White/Orange 6 Reader Run+

We toggled in a program that increments the AC and sends the contents out the serial console port. It worked OK with the VT220 configured for 110,E,7,2. We toggled in the loopback program, and what we typed on the keyboard was displayed on the screen. That means that a lot of the I/O and the serial cable that we made is working OK. We tried the same with a Laptop, USB/Serial cable, and Warren's RS-232/Current Loop converter. The loopback did not work. A different serial cable worked better, but not correctly. We tried a different terminal emulator and got it to work.

The DCA instruction is not working reliably. We will need to fix that before the BIN loader will work. This broken instruction will prevent loading BIN formatted paper tape images of the diagnostics.

We fiddled with DCA instructions and found that the MB is not being cleared and the AC is ORed into the MB and then stored in the target memory location. The memory location should be cleared and the contents of the AC should replace the memory. We need to check the #MEM STROBE ENABLE signal that inhibits the memory cycle, and probably is not.

6-Oct-24

Grand did some more testing and verified that the DCA instruction is not clearing the MB before ORing the contents of the AC into the MB. He also found that the JSR instruction is doing the same thing, and likely has the same cause. On Wednesday we will use a 'scope to look at the #MEM STROBE ENABLE signal when a DCA or a JSR instruction is executing. It is interesting that the front panel forces the processor to execute a DCA instruction when storing the contents of the switches in memory. That seems to work OK.

9-Oct-24

We need to look at the #MEM STROBE ENABLE signal when a DCA or a JSR instruction is executing. This signal originates on schematic page D-8P-0-9.

We measured the voltage drop on the diodes and transistors on the S111 in slot PC31 and found that D10 had a voltage drop of about 200mV in both directions. This defect was holding pin P at a low voltage and preventing the inverter output at pin N from driving the MEM STROBE ENABLE signal inactive. We replaced the defective diode with a NOS D-664 and now the DCA and JMS instructions work. 

Grant started testing the remaining instructions and found that memory address 0024 did not work. We looked at Schematic page BS-D-8M-0-13 for the Y Axis Memory Selection and determined that the G603 in slot MP6 was the only FlipChip that could cause this problem. We replaced it with a spare and now memory location 0024 is working.

Grant finished testing the Memory Addressing Modes and EAE instructions. All work OK. There are a few IOT instructions for the serial console that we still need to test.

12-Oct-24

The Teletype made some horrible noises while we were using it, so we need to fix that.

16-Oct-24

Grant wrote and toggled in a core memory test for the Zero-Page, the first 128 words of core memory. The core memory test ran for about 30 minutes without errors. That was at least 70,000 passes of the test.

We connected a VT220 terminal to the console cable and ran a loopback program. It worked OK, so we know that the console serial interface is working OK.

We connected an FTDI USB/RS-232 cable to Warren's RS-232/20mA current loop adapter. The received characters didn't match what we typed, and it even looped back characters without the PDP-8 running. We changed to a Prolific cable and the serial console worked OK.

Grant will reverse engineer Warren's RS-232/20mA current loop adapter and repair the Reader Run circuit.

Grant found during his memory testing that the JMS instruction is overwriting itself with zeros. We decided to look at the MEM STROBE ENABLE signal that we fixed last week. For both the DCA and JMS instructions it is working OK. We looked at the JMS and JMS# signals and both are OK. The JMS signal from the R151 decoder is noisy when other instructions are running. DEC put a capacitor on the signal to kill the noise, so maybe the capacitor is bad?

Grant's memory test showed that memory addresses in the range of 17xx did not work. We replaced the G603 in slot MP2 and now all memory works again.

16-Oct-24

Grant repaired Warren's RS-232/20mA converter. Now Reader-Run works and we can use the adapter for loading paper tape images.

We loaded the BIN loader using the Warren's RS-232/20mA converter. Unfortunately the JMS instruction is still broken, so we can't run the BIN loader.

We loaded MAINDEC 802 Memory Checkerboard High. We configured it for memory field 0, and ran it. We let it run for several minutes without errors.

We studied the misbehavior of the JMS instruction and decided that it was behaving like it was handling an interrupt not executing the JMS instruction. The signal /INT ACK determines how the JMS instruction behaves. It comes from the S203 triple-flip-flop in slot PC36. We swapped it with a spare and the JMS instruction is now behaving better. We still need to test the JMS instruction more before we can declare victory.

23-Oct-24

We are testing the JMS instruction to see if we have a hardware problem, or an operator error. We tried a few combinations with some working and some not.

We tried the JMS example in the Table 2-1 Maintenance Manual. With the JMS instruction at address 0021 and the target at 0100 the JMS works OK.

We tried a NOP at 7000 and a JMS instruction at address 7001 and the target at 7070. With SINGLE STEP on we pressed START and then CONT. The JMS did not work. It overwrote the JMS with 0000, stored the return address in 0000, and set the PC to 0001.

We noticed that if the first instruction is a NOP, and we press START and then CONT the JMS stores the return address at 0000 and sets the PC to 0001. It looks like the problem is with the CONT behavior differing from START. We toggled in a short program that did a JMS, returned from the JMS, and halted. That program worked OK.

The return spring in the START switch doesn't return the switch all the way. If the switch is left part way returned the JMS instruction works OK. If it is manually returned all the way the JMS instruction does not work. We need to repair or replace the START switch.

We tried to load MAINDEC-801-1 PDP-8 Instruction Test Part-1 from a RIM format paper tape with a Teletype. We found a tear in the tape during loading, so we may have errors. The diag did not load, so there is something wrong with the RIM loader.  We checked the RIM loader in memory and the contents are OK.

26-Oct-24

We single-stepped the RIM loader and loaded a little RIM format paper tape image that Grant created. It looks like the SNL instruction that is used in the RIM loader is not working. We tested the SZL and SNL instructions with LINK set and cleared, and both instructions are broken for both conditions of the LINK. We checked the R111 FlipChips in slots PD27 and PD28, and the transistors and diodes looked OK. After we wiggled the FlipChps in their sockets the SZL and SNL instructions started working.

We connected the Teletype and and uploaded a RIM formatted file. Bit-8 does not work. looks like the USART is broken.

30-Oct-24

We needed to fix the serial console USART. Bit-8 from the Teletype was not being transferred to the AC. Grant looked at the bit-0 output pin from the UART and the voltages were OK when bit-8 from the Teletype was either a 0 or a 1. He looked at the input pin to the AC bit-4 and the voltage was always -14V when bit-8 from the Teletype was either a 0 or a 1. We measured the resistance from the backplane connector pin for UART bit-0 to the backplane connector pin on the memory wing for the cross-wing ribbon cable. The resistance was just a few Ohms, so OK. We measured the resistance from the backplane connector pin for UART bit-0 to the backplane connector pin on the processor wing for the cross-wing ribbon cable. The resistance was infinite, so there is a problem with the ribbon cable connector. We measured the resistance from the backplane connector pin for UART bit-0 to pin A on the cross-wing ribbon cable where it plugs onto the memory wing, then to the start of the ribbon cable wire, then to the end of the ribbon cable wire, and then to the gold finger on the processor side. The resistance was about 200 Ohms, so OK. We measured the resistance from the backplane connector pin for UART bit-0 to the backplane connector pin on the processor wing for the input to the AC. The resistance was just a infinite, so the problem is between the gold finger and the backplane connector or the ribbon cable. We cleaned the gold fingers on the ribbon cable and now all of the data from the Teletype gets to the AC.

We ran the MAINDEC-801 Instruction Test. It ran, but not in the correct instruction sequence. We reloaded the diagnostic and put a HLT instruction in location 0001 to stop the processor if the JMS instruction failed. The diagnostic immediately halted at 0001 with 0035 in location 0000, the return address.

We keep seeing the diagnostic halt at 0442. It should be doing an ISZ and it didn't. The memory location should contain 2244 and actually contained 0160. Maybe we have a memory problem at that location. We can manually deposit all bits to that location.

We replaced the instructions in locations 0456 through 0524 with NOP to delete the JMS testing. Now the diagnostic runs OK. 

2-Nov-24

We ran the MAINDEC-801 Instruction Test to see if the JMS instruction works when the system is cold. It does, but it halted at 1062 with the MB containing 7402, the AC containing 0376, and the LINK on. This shows a problem with the JMS instruction when interrupts are enabled.

We put the original S203 FlipChip that we replaced last week back in slot PC36, reloaded Maindec-801, and ran it. It halted at 0205 with the AC=0000 and the LINK off.

After lots of experiments we thought that the the state machine is stuck in the FETCH cycle. After checking the diodes and transistors on the boards that implement the state machine and watching the signals on a 'scope, we learned that almost all instructions only use the FETCH cycle. Only JMS, DCA, ISZ, TAD, and AND have an EXECUTE cycle. We tried some instructions with indirect addressing and we can see the FETCH, DEFER, and EXECUTE states all working, so the state machine is working OK.

We spent a lot of time looking a machine state related signals, but didn't find anything that could cause problems with the JMS instruction.

9-Nov-24

The return spring in the START switch is broken and will not return the switch to the inactive state. Grant toggled in a JMS-JMP test and it works OK if the START switch is held down. If the START switch is moved to the inactive state the the test fails. The JMS instruction will behave like an interrupt if the START switch is moved to the inactive state. 

We decided to look at the signals from the START switch as they flow through the processor. We looked at SP1 and KEY ST+DP+EX on the R602 in slot PC20 on sheet 5 of the processor schematics. The KEY ST+DP+EX signal corresponds to the position of the START switch. The SP1 pulses to ground just once when the START key is pressed. This looks OK.

We looked at pins D & E of the R107 in slot PD26. The INT ACK signal was never active. Pin D is an open-collector signal shared with other sources and has a 1 MHz signal that is active with the START switch down and inactive with START switch up. The 1 MHz signal is coming from the logic F(1)+JMS+MB3(0). When the START switch is deactivated the JMS is interpreted as an interrupt and it stops executing the JMS loop. This looks OK.

We looked at pins P, R, and U of the R602 in slot PC20. We saw the 0->MB signal on pin U only when TB2 was active and F(1)+JMS+MB3(0) was active. This looks OK.

We looked at pins R, S, and T of the R603 in slot PD21. We saw the TB2 signal on pin R, but didn't see the F(1)+JMS+MB3(0) signal on pin S. We verified that PD26S and PD21D are connected. Wiggling the scope lead fixed this problem. The output on pin T is active when the TB2 and the F(1)+JMS+MB3(0) signals are active. This looks OK.

Looking at processor schematic page 8. We looked at pin K on the R602 in slot PC20. We saw a single pulse from the SP1 and KEY ST+DP+EX signals, and then a regular signal from executing the JMP instruction.

We looked at pin F of the R603 in slot PC21. The 0->MA 5-11 was never active. This looks OK.

We looked at pin M of the R602 in slot PC21. This signal is active every time an instruction is executed, so it looks OK.

We looked at pin F of the R602 in slot PC22. This was always inactive, so it looks OK.

We looked at pin M of the R602 in slot PC22. This signal is active every time an instruction is executed, so it looks OK.

We looked at pin T of the R602 in slot PC22. This was always inactive, so it looks OK.

We looked at the wiring modifications that were done to the clock circuit on page 9 of the processor schematics. In the original design the R405 Clock FlipChip was in slot PB35 with the output on pin D wired to pin D of the R202 in slot PB34.

13-Nov-24

Connect the Logic Analyzer to the instruction Register Decoder circuit so we can see what instructions are executing. Trigger on T1?

Previously we noticed noise on the JMS and JMS# signals from the R151 in slot PB27. DEC added a capacitor on the Wire-Wrap tails of pin L/M of the R151 to reduce the noise. Maybe the capacitance has diminished with age and the noise is causing problems?

We still think that a JMS instruction is being processed as an interrupt. The INT ACK signal determines if the JMS is really an interrupt. We can trigger the 'scope on the JMS signal on pin S of the R151 in slot PB27. We should also look at the #JMS signal on pin L of the S107 in slot PB26, and the INT ACK signals on pins E & F of the S203 in slot PC36. If we then make a loop with the JMS instruction in it, and put a HLT instruction in memory location 1. When the processor halts at 0001 we should be able to determine why it processed an interrupt instead of a JMS.

Doug Ingraham suggested using the Margin switches and power supply to force the intermittent JMS problem to be a hard failure. That might make it easier to track down the fault. Increasing the +10V supply will expose low-gain transistors. Decreasing the +10V supply will expose high-leakage transistors. Increasing and decreasing the -15V supply increases and decreased the output signal voltage. Decreasing the -15V supply below -18V may damage components. The system should perform OK when the +10V supply is adjusted +/-5V, and the -15V is adjusted +3V/-0V.

We are still chasing the misbehaving JMS instruction.

The return spring in the START switch is weak and will not return the switch to the inactive state. We found that the JMS instruction will work OK if the START switch stays in the active state. When the START switch returns to the inactive state the JMS instruction will behave like an interrupt. We will investigate more about what is happening when the START switch goes inactive.

We am thinking of triggering the 'scope on the RUN signal, putting a HLT instruction in memory location 0001, and making a JMP-JMS loop. This should behave OK until the START switch is lifted to the inactive position. Then we can chase the signals that change a JMS into an interrupt and maybe determine what is broken.

The system was modified by the previous owner.

See schematic page BS-D-8P-0-9. The W501 Schmitt Trigger in slot PA36 has been replaced by an R302 Delay. The circuitry at the top left of schematic page 9 has been modified, and we don't understand all of the changes. There is an R303 Integrating One-Shop in the normally empty slot ME29. Two gangling wires are connected to the capacitors on pins K & L. There is also a dangling wire connected to the level input on pin U. The input pin T and the output pin D are wired into the processor. We think that the R303 and R302 are wired together. We need to finish reverse engineering this modification.

The front panel switches usually work OK so we have been ignoring this modification. We have a spare W501 so we could undo this modification.

See schematic page BS-D-8P-0-9. Normally there is an R405 clock FlipChip in slot PB36. The R405 was moved to the empty slot MF29 and an R602 Pulse amplifier was installed in slot PB36. The R602 is spliced in between the R405 and the R202 in slot PB34. The CLOCK output on pin D of the R405 is wired to PULSE INPUT on pin H of the R602. The LEVEL INPUT on pin J of the R602 is wired to the RUN STOP signal. The Gated CLOCK signal from the R602 is wired to where the original CLOCK signal goes on pin D and pin U of the R202 in slot PB34. I think that the idea of this modification was to turn off the CLOCK signal when the RUN STOP signal goes inactive. The gating of the CLOCK signal by the R602 is not working even though the input signals look OK.

We am not sure what they were trying to accomplish with the CLOCK modification. The TG flipflop will only toggle when the RUN(1) and PAUSE(0) signals are active, so what does turning off the CLOCK signal do? We are thinking of undoing this modification.

16-Nov-24

We continued reverse engineering the modifications done to the processor. We haven't finished yet.

We are still working under the assumption that the JMS instruction works correctly until the START switch is raised to the inactive state, and then the JMS instruction gets processed as an interrupt.

We toggled in a JMP-JMS loop and put a HLT instruction in memory location 0001. When the START switch is lifted to the inactive state, the processor will do an interrupt instead of a JMS instruction. We triggered the 'scope on the RUN signal, and started looking at the signals that change when the START switch is lifted.

We expected to see the INT ACT signal go active just before the processor halted. It didn't, so the processor was not doing an interrupt instead of a JMS. So now we have proved that an interrupt is not happening even though the PC is getting set to 0000 during a JMS. We are now on the hunt for the signal that is causing the problem.

Schematic page BS-D-8P-0-7 shows the logic flow when instructions are executed. For the JMS instruction, it starts with the Fetch phase. The MEMORY STROBE signal goes active to get the instruction from core memory. The INT ACK signal is evaluated to determine if the instruction is a JMS or a hardware interrupt. In our case the instruction is a JMS. We have already proved that the INT ACK signal is inactive, so that is OK. The contents of the high order bits of the MB are transferred to the IR so the instruction can be decoded. Bits 5-11 of the MB are transferred to the MA in preparation for writing the return address into the first memory location in the subroutine.

We think that this is where the problem is. We think that the contents of the MB are not being transferred into the MA, so the MA contains zeros and the JSR target address is 0000. 

23-Nov-24

After several hours of debugging Lou came to visit. We demonstrated our debugging to Lou and explained what we had found so far. While explaining what we had done so far we noticed that the contents of the MB would clear when the START switch was deactivated even when the processor was not running. This could explain the problem we are looking for because the contents of the MB would get cleared when the START switch was put in the inactive state.

We looked at one of the flip-flops that make up the MB register and its state matched the changes we see on the front panel. We looked at all of the signals that can load data into the MB. When we put the 'scope probe on the 0->MB signal, the position of the START switch no longer affected the contents of the MB. We noted that the 0-MB signal on pin PC20U goes to ground when active, but only goes to -1.7V when inactive. The S602 pulse amplifier in slot PC20 drives the 0->MB signal. We swapped it for a spare R602 (weaker pull down resistors ) and the system works OK with the START switch in either position. The inactive 0->MB signal should go lower when it is in the inactive state.

We loaded and ran MAINDEC-801 Instruction Test Part 1. It halted at 0442 when an ISZ instruction failed. We tried some toggle-in ISZ tests, and they worked OK. We reloaded MAINDEC-801 Instruction Test #1. We replaced the temporary R602 with another spare R602 and this time it ran OK. The START switch does not affect the behavior. The 0-MB signal is going to -3.7V when inactive.

27-Nov-24

We loaded and ran MAINDEC-08-D01A PDP-8 Instruction Test Part 2A. The diagnostic only takes about 15 seconds to run. It didn't halt, so all of the tests ran OK.

We loaded and ran MAINDEC-08-D02B PDP-8 Instruction Test Part 2B. We ran the TAD diagnostic for 15 minutes. It didn't halt, so the test ran OK. We ran the rotate diagnostic for 15 minutes. It didn't halt, so all of the tests ran OK.

We loaded and ran MAINDEC-08-D03A Basic JMP-JMS Test. It didn't halt, so the test ran OK.

We loaded and ran MAINDEC-08-D04B Random JMP Test. It didn't halt, so the test ran OK. A single pass takes 10 seconds and "04" on the console.

We loaded and ran MAINDEC-08-D05B Random JMP-JMS Test. It didn't halt, so the test ran OK. A single pass takes 12 seconds and "05" on the console.

We loaded and ran MAINDEC-08-D07B Random ISZ Test. It looks like the diagnostic didn't load correctly. There were a number of memory locations where bit-10 was set where it should not be, and it added a HLT to the instruction.

30-Nov-24

We loaded and ran the high memory version of MAINDEC-08-D1B2 Memory Address Test. It didn't halt, so the test ran OK. 

We loaded and ran the high memory version of MAINDEC-08-D1L2 Basic Memory Checkerboard. It didn't halt, so the test ran OK. 

We loaded and ran the high memory version of MAINDEC-08-D1MA Memory Address Test. It didn't halt and printed 11 on the console after each pass, so the test ran OK.

4-Dec-24

We loaded FOCAL-69 from a paper tape image. It actually loaded and ran correctly. This means that most of the processor is working correctly.

11-Dec-24

We worked on the acrylic covers for the PDP-8 today. They are made from a light blue opaque acrylic top cover and dark blue translucent acrylic sides. A grove was milled into the top cover to accept the side cover, and the two parts were glued together. The top cover sits on the FlipChip bay hinge in the back and on the FlipChip bay handle on the front. This puts a lot of stress on the glue joint and eventually cracks it. Someone in the past had glued the covers back together with contact cement which made a big mess. We spent a long time picking and scraping the contact cement out of the glue joint and eventually got it clean. We used acrylic glue to put it back together and reinforced the joint by gluing a 1/2" square strip of acrylic inside of the glue joint. We also 3D printed supports that we will attach to the chassis and will support the bottom edge of the convers. It looks good now and should not crack again.

14-Dec-24

We ran MAINDEC-08-D0BA-D PDP-8 Instruction Test Part 3B EAE. It ran OK for more than an hour and then halted at 0461. It was nice to see the MQ lights on the front panel flashing.

No one has documentation for MAINDEC-08-D0BA. We used the D8TAPE program to disassemble a binary image of the paper tape. We will add comments to the disassembled source code and see if we can determine what the test was doing when it halted. It is possible that this issue is actually a memory problem because the diagnostic would not restart without reloading it. After reloading and restarting the diag it halted at 0461 again.

There is no HLT at address 0460. That address contains an SZL instruction, 7430. If that memory location picked up bit-10 and changed the instruction to a 7432, it would halt there. We will check that on Wednesday.

18-Dec-24

Core location contained 7672 when it should contain 7430. It picked up bits 4, 6, & 10. We looked at core locations from 0444 to 0460 and found that core location 0455 contained 3773 and should contain 3761. It picked up bits 6 & 10. Bit 4 was supposed to be on so we would not see the the bit picked up. Core location 0456 was 7753 and should be 7501. There were four words in core locations 0455-0460.

We reran MAINDEC-08-D0BA and quickly saw an error message from the DVI test. It is likely that more memory locations were corrupted. When we tried to reload MAINDEC-08-D0BA we found that the BIN loader was corrupted. We reloaded the BIN loader in RIM format, and then tried to reload MAINDEC-08-D0BA. We also found that the RIM loader was corrupted.

Address Contents Should Be

7756 7272 6032
7757 7273 6031
7760 5357 5357
7761 7276 6036
7762 7356 7106
7763 7006 7006 (OK)

We decided that the G203 address decoder for the condition where MA6(1) was a 1, MA7(1) was a 1, and MA8(0) was a 0, MA8(1) was a 1 was the faulty FLipChip. We pulled the G203 from slot MC15, cleaned the gold fingers, and reinstalled it. We reloaded the RIM loader, and tried to reload the BIN loader. The RIM loader was quickly corrupted in the same fashion as before. 

We cleaned the gold fingers on all of the G203. Grant deposited 0000 in core locations starting at 0000. These locations contained 5252 when read back. It is not obvious from the schematics what part of the memory circuitry would affect every other bit. The memory started working OK, and failed again when we ran the RIM loader.

We wiggled all of the margin power switches and now the memory seems to be working. We reloaded the RIM and BIN loaders, and then MAINDEC-08-D0BA. The EAE diag ran for 30 minutes without fault. We declared victory and went home.

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