Making a Posibus Periperal Emulator

Contact mike@ricomputermuseum.org for details.

Introduction:

Many of the PDP-8 systems that are rescued are missing the peripherals, or the peripherals require extensive restoration. I am attempting to use an Emcraft Linux SmartFusion Evaluation Kit to make a Posibus Peripheral Emulator^tm. I chose the SmartFusion FPGA because it contains a Cortex M3 processor in a hard core. That eliminates the need to invent an interface between the FPGA and a processor. The Emcraft evaluation board for the SmartFusion has enough I/O to emulate 8-bit devices that send data to the processor. There is not enough I/O on the evaluation board to support receiving data from the processor. A second generation of the Posibus Peripheral Emulator^tm will use the Emcraft SmartFusion SOM Starter Kit that has enough I/O to emulate any Posibus peripheral, including disks and tapes.

Many thanks need to go to Vincent Slyngstad for supplying the Posibus Interface FlipChips, Warren Stearns for guidance and advice on the logic level translators, Ray Zeller for supplying the DS3862 and DS3662 chips to drive the Posibus, and Kent Meyer and Vladimir Khusainov and the rest of the team at Emcraft for help with creating the Linux device driver and Linux paper tape reader emulator application.

The Plan:

The first project phase was making an interface from the +5.0VDC TTL signals that are used in the PDP-8/L to the +3.3VDC TTL signals that are used in the Actel SmartFusion FPGA. Vincent Slyngstad made FlipChip interface boards that connect the Posibus signals to two 34-pin ribbon cables. You need three double-sided Flip-Chip interface boards for the complete programmed I/O Posibus. The Posibus signals go from the Flip-Chip interface boards, through the ribbon cables to the Wire-Wrap board, through 74LVC245 ICs to translate the logic levels to something that the FPGA can handle. These 3.3V ICs will be powered from the Emcraft Evaluation Board. The signals from the FPGA go through DS3862 and DS3662 chips, back through the ribbon cables, and drive the open-collector Posibus.

The Emcraft Evaluation Board has an Actel SmartFusion A2F200-FG256 FPGA with an ARM CORTEX M3 processor in a hard core, 16 MB RAM and 8 MB of flash memory so that it can run their port of uC Linux. I created a simplified version of the paper tape reader controller logic in the FPGA. This logic includes the I/O device code decoding, gating for the three IOT pulses, the paper tape reader flag flip-flop, a signal to drive the skip-bus signal, 8 bits of paper tape data, and a signal to enable the data bus drivers. These functions run at "hardware speed" and do not involve the processor. The rest of the paper tape reader is emulated by the Linux device driver and the Linux application. These functions can be much slower than the hardware.

The PDP-8 6014 RFC (Reader Fetch Character) instruction puts a 6-bit I/O device code on the Posibus and then an IOT 4 strobe. The 6-bit I/O device code is anded with the IOT and then generates an interrupt that is handled by the paper tape reader controller Linux device driver. The Linux device driver interacts with the paper tape reader controller logic in the FPGA, and provides a Linux device for the paper tape reader emulator application, and handles the interrupt from the RFC instruction. The paper tape reader emulator application reads a character from the paper tape image file in flash memory, writes the character to the paper tape reader device, sets the reader flag flip-flop, reads another character from the paper tape image file in flash memory, writes that character to the paper tape reader device and goes to sleep. When the device driver receives the interrupt from the RCF instruction it wakes the application which reads another character from flash and writes it to the paper tape reader device, and goes back to sleep. The double-buffering improves the performance of the emulated reader.

Progress Reports:

12/27/12

The logic in the FPGA decodes the 01 device code for the High-Speed Paper Tape Reader correctly. The RRB (Reader Read Buffer) 6012₇ instruction clears the Reader Flag flip-flop in the FPGA. The RFC (Reader Fetch Character) 6014₇ instruction clears the Reader Flag flip-flop in the FPGA and generates an interrupt to the paper tape reader device driver.

With the DS3662 Open Collector Trapezoidal driver IC installed and the Skip Bus\ signal wired to the FPGA, the RSF (Reader Skip Flag) 6011₇ instruction will skip when the Reader Flag flip-flop is set. Programs that read from the High-Speed Paper Tape Reader execute a RSF instruction followed by a JMP -1 instruction. When the Reader Flag flip-flop is cleared the JMP -1 instruction is executed and the program loops. When a character is available the Reader Flag flip-flop is set the Skip Bus\ signal is driven low and the processor skips over the JMP -1 instruction and then reads the character from the High-Speed Paper Tape Reader. Reading the character causes the Reader Flag flip-flop to be cleared.

01/02/13

I finished wire-wrapping the interface board and updated the firmware on the FPGA to the latest version. The current firmware will only send a single file. I configured the firmware to send Focal language interpreter because it is a large paper tape. Loading Focal from a Teletype at 10 characters per second takes about 13 minutes. Loading from the high-speed paper tape reader at 300 characters per second takes about 25 seconds. My relatively inaccurate timing was about 2-3 seconds for loading Focal from the emulated paper tape reader. That should be somewhere about 2496 to 3744 characters per second. I need to do some more investigation to see if the speed is limited by the PDP-8/L or the emulated paper tape reader. This is actually much faster than reading Focal from a DECtape (a block oriented magnetic tape).

Next Step:

Update the paper tape reader emulation application so that it asks for the file name of the paper tape image, and load lots of paper tape images onto the flash memory.

Future Work:

Change from the Emcraft A2F-LNX-EVB board to the Emcraft SmartFusion SOM kit. This will let me use more than 90 FPGA I/O pins so I can emulate just about any peripheral. It should be possible to emulate Data-Break (DMA) peripherals like tapes and disks.

Click on the image for a larger view.

The PDP-8/L is in the background.

I used ribbon cable interface boards from Vincent to connect the Posibus to the Wire-Wrap board.

The Emcraft A2F-LNX-EVB SmartFusion Evaluation kit is in the foreground at the left.

Click on the image for a larger view.

The receiver chips are 74LVC245 and the transmitter chips are a DS3862 and a DS3662.

The Emcraft A2F-LNX-EVB SmartFusion Evaluation kit is in the foreground.