PDP-9 Restoration Blog 2024

Go to the earlier restoration blog.

1/3/24

We decided to look at the PC09 Reader Timing as described in the System Adjustment Manual in section 4.5. We punched a short paper tape of alternating ones and zeros, and made it into a loop. We toggled in a short program to continuously read the paper tape loop. We need to adjust the G904 so that all eight channels of the paper tape reader have 50% duty cycle, or within 5% of 50%.

We connected a 'scope to the outputs of the G904 Photo Amplifier Module. The signals look strange, and are not square waves. We happened to look at the power supply voltages and found that the -15VDC is OK, but there is nothing on the _10VDC. The G905 uses +10VDC everywhere, so the missing power supply voltage would really make a mess of things.

There is +10VDC on the reader lamp, so the voltage is getting to the reader. I don't see how +10VDC gets from the power connector on the back of the reader to the backplane. There is a single yellow wire from the +10VDC red power connector to the lamp, but no connection to the +10VDC on the backplane. There is a blue/white wire going from the -15VDC on the backplane to the B pins on the reader backplane. I see nothing to supply +10VDC to the backplane. We can look at how the reader on the PDP-12 is wired for comparison.

After some further study it looks like the +10VDC and the -15VDC for the logic in the paper tape reader comes from the PDP-9 I/O controller and through the I/O cable. We will check that Saturday.

1/6/24

The +10VDC and -15VDC power for the paper tape reader logic is supplied from slot A17 in the I/O chassis. The W023 flipchips on the ends of the paper tape reader control cable have jumpers installed to pass the +10VDC and -15VDC power to the paper tape reader logic. The original flexprint cable delaminated, so it was replaced by modern ribbon cable. Margin Switch #3 supplies power to slots A10-A22. We need to insure that the +10VDC and -15VDC power is present on I/O slot A17, inspect the W023 flipchips to insure that the +10VDC and -15VDC jumpers are intact and that the ribbon cable wires for the +10VDC and -15VDC power are OK. We need to measure the +10VDC and -15VDC power on the punch end of the cable to make sure that the the +10VDC and -15VDC power is present. Then we can check that the +10VDC and -15VDC power is present in the paper tape reader logic.

The +10VDC fuse for switch #3 in the I/O chassis was blown. We replaced the fuse, and now we have both +10VDC and -15VDC at the paper tape reader. We ran a toggle-in program that reads the paper tape in ASCII mode. We looked at the G904 flipchip feed-hole signal on pin A1N on the paper tape reader. The signal should be a square wave, but is really noisy. We looked at the output of the photosensor for the feed hole on pin B1D. The signal is also really noisy. Moving the paper tape feed wheel a little makes the signal more negative, so maybe the wheel position needs to be adjusted. We punched another 0/1 paper tape loop on a different Teletype, and this tape had much more even spacing for the holes and works much better. We adjusted the G904 for 50% duty cycle on the holes. It really only needed a slight tweak.

The console can display the RDR state, which is the register in the paper tape controller in the I/O controller. That looks like it is working OK.

MAINDEC-9A-D0BA ISZ Test loaded and ran OK.
MAINDEC-9A-D0CA Memory Address Test loaded and ran OK.
MAINDEC-9A-D0DB JMP Self Test loaded and ran OK.
MAINDEC-9A-D0EA JMP-Y Interrupt Test loaded and ran OK.
MAINDEC-9A-D0FA JMS-Y Interrupt Test loaded and ran OK.
MAINDEC-9A-D1AA PDP-9 Basic Memory Checkerboard Test loaded and ran OK on the first try.
MAINDEC-9A-D1BA PDP-9 Extended Memory Checkerboard Test loaded and ran OK.

It was running diagnostics so nicely we decided to see if the ADSS monitor would boot from DECtape. The first two DECtapes that we tried got many read errors, but the tape that includes FOCAL actually booted! So now we have the only PDP-9 on the planet that runs again. 

We still need to repair the motor controller on the third DECtape drive so that we can compile and run FORTRAN-II programs for a demonstration. 

1/10/24

The PDP-9 booted ADSS after a few IOPS4 errors. We should reformat and recreate all of the ADSS tapes so it will behave better.

We borrowed a working G850 from the bottom TU55 DECtape drive on the PDP-8/I and installed it in the left TU55 DECtape drive in the PDP-9. Both spindle motors work OK now. We tried to list the directory of several PDP-9 DECtapes. The tapes shoe-shined a lot, and the message "SYS DEV ERR TRY AGAIN" was displayed on the console. We even tried a known good DECtape that was formatted and written on the bottom right drive on the bottom left drive. The behavior was the same. After putting the DECtape back on the bottom right drive it worked perfectly. So it looks like there are more problems with the bottom left TU55 DECtape drive than just the G850 motor controller flipchip.

1/17/24

The bottom right DECtape is the only one that will work reliably. ADSS did boot from that drive, but the other two drives are getting lots of errors. Time to reseat the cables and relay boards. Well, that didn't make any difference.

Just to finish our processor debugging work we decided to run the rest of the diagnostics. 

MAINDEC-9A-D01A Instruction Test Part 1 loaded and ran OK.
MAINDEC-9A-D02A Instruction Test Part 2 loaded and ran OK.
MAINDEC-9A-D0CA Memory Address Test loaded and ran OK.
MAINDEC-9A-D1FA PDP-9 Extended Memory Address Test loaded and ran OK.
MAINDEC-9A-D2BA PDP-9 TTY Test loaded and ran OK.

All of the processor and memory tests have been successfully run within the last two weeks.

The MAINDEC-15-D4AF TC-59 Instruction Test has a good data-break test. We need to convert two cut PDP-15 I/O cables into a single BC9A I/O cable so we can daisy-chain the I/O bus from the TC02 to the TC59 controller. That sounds like a good project for today.

We unsoldered the flipchips on the end of a cut BC15A cable, and trimmed the length of the cable on a cut BC09A cable. We studied the circutry on the BC15A FlipChips, and they will work for a BC09A cable. The BC15 cables don't have the diode terminator logic that the BC09 cables have. It should work anyway.

1/20/24

It was a busy day at the Museum, so we didn't have much time to work on the PDP-9. The machine ran for several hours for demonstrations, and to format 3x DECtapes. We will write ADSS images on the DECtapes using Mike's PDP-8/e.

1/24/24

Our PDP-9 didn't come with any of the special I/O cables to connect the processor to peripheral controllers. The Kennett Classic Computer Museum donated a long PDP-9 I/O cable, and Mike bought a long PDP-9 cable, and a short PDP-15 cable on eBay. Mike also bought a cut PDP-9 cable and a cut PDP-15 cable. Today we made a short I/O cable by soldering the end of the PDP-15 cable onto the cut PDP-9 I/O cable. It may not be perfect, but it should work well enough so we can use both tape controllers. 

We tried to boot ADSS on the PDP-9, and found that the only switch on the console that works is the RESET switch. We probably have a problem with the Control Memory timing circuitry, so that should not be too difficult to debug.

1/27/24

We finish soldering the I/O Cable. That will let us start work on the TU20 7-Track Magnetic tape Drive. We will test it after we get the processor working again.

Determine why the PDP-9 doesn't respond to any console switches. We rotated the REPEAT SPEED switch to position 1, and the console switches worked slowly. The console also worked a incrementally faster speeds, including position 5, which is full speed. We reloaded the ADSS bootstrap from paper tape, but the ADSS DECtape is getting MR (Mark Track) errors when booting. After several tries of different DECtapes we finally got ADSS V4E to boot. ADSS V4E is a PDP-9 only version of ADSS.

The project for this weekend is to recreate the ADSS V5A and ADSS V5B DECtapes on Mike's PDP-8/e.

1/31/24

We haven't been able to make new ADSS tapes on Mike's PDP-8/e. We suspect that the new virus checking software is preventing the Windows program from sending characters out the serial port. We will try a different PC to see if the behavior is different.

ADSS V4E booted from the top right DECtape after about 10 tries. ADSS V5E also booted from DECtape. We loaded and ran the "HELLO WORLD" program.

We installed the BC09 cabled between the TC02 DECtape and TC59 Magnetic Tape controllers. The system still booted ADSS V5A from DECtape, so the cables didn't break anything. All of the lights on the TC59 indicator panel are out except for Parity in the WRITE BUFFER and bit-7 in the CRC. Saturday we will execute some TC59 IOT instructions to make sure that we can interact with the TC59 controller. Then we will run the TC59 controller diagnostics, especially the Data-Break test. 

2/3/24

ADSS 5A booted on the first try. I was planning to run SGEN to build a new system tape, and the console started printing strange characters.  It would not reboot ADSS. We single-stepped the DECtape bootloader, and found that memory locations 17750 and 17754 were missing bit-0. This looks like a memory addressing issue, so it should not be too difficult to debug.

We filled all of memory with 777777 and then examined memory to see if all locations contained 7777777.

Address Contents
00000 377777
00001 777777
00002 777777
00003 777777
00004 377777

We did some experimenting by looking for memory locations that had bit-0 set to zero. We found that any memory address with both bit-16 & bit-17 set to zero had a zero in bit-0. Much of the memory address circuitry has individual buffers for each bit, so it is unlikely that is where the fault is.  The problem can't be in the Sense Amplifier, because some of the words have a working bit-0. The Word Selection circuitry only uses bits 6..13. The Digit Drive circuitry uses bits 13..17 so that is likely where the problem is.

We swapped the G219 FlipChips in slots AB07 (bit-0) and AB08 (bit-8) and the problem moved from bit-0 to bit-8. So the problem is the G219 that is now in slot AB08. We put the G219 from slot AB08 back in slot AB08 and replaced the G219 in slot AB07 with an untested spare. Now all of the memory works OK. ADSS booted OK.

To make sure that the TC02 to TC59 I/O cables that we installed last week work OK, we ran MAINDEC-15-D4AC TC59 Magnetic Tape Control Instruction Test. Subtests 00-03 ran without errors. Subtest 04 tests additional IOT instructions, and expects tape drive 0 to be online and ready. Our TU20 tape drive was not connected, so it halted here. Tests 00-03 test all possible combinations of data on the I/O cable, so it looks like they work OK.

2/10/24

The PDP-9 was used to make a short movie this week.

Today it booted ADSS on the first try and ran the Hello World program, so everything is OK.

2/14/24

Today it booted ADSS after a few tries and ran the Hello World program after a few tries, so everything is OK.


Maindec Diagnostics

MAINDEC-9A-D0BA ISZ Test, 1/6/24

MAINDEC-9A-D0CA Memory Address Test, 1/17/24

MAINDEC-9A-D0DB JMP Self Test, 1/6/24

MAINDEC-9A-D0EA JMP-Y Interrupt Test, 1/6/24

MAINDEC-9A-D0FA JMS-Y Interrupt Test, 1/6/24

MAINDEC-9A-D01A Instruction Test Part 1, 1/17/24

MAINDEC-9A-D02A Instruction Test Part 2, 1/17/24

MAINDEC-9A-D1AA PDP-9 Basic Memory Checkerboard Test, 1/6/24

MAINDEC-9A-D1BA PDP-9 Extended Memory Checkerboard Test, 1/6/24

MAINDEC-9A-D1FA PDP-9 Extended Memory Address Test, 1/17/24

MAINDEC-9A-D2BA PDP-9 TTY Test, 1/17/24

MAINDEC-9A-D3BB TC02 Basic Exerciser, 1/1/22

MAINDEC-9A-D3RB TC02 DECtape Random Exerciser, 12/14/19

MAINDEC-9A-D7AD PDP-9 Basic Exerciser (no punch or tape reader), 5/18/19

MAINDEC-15-D4AF TC-59 Instruction Test, 12/3/22


The boards replaced in the PDP-9 processor so far are: 

B131 Adder in slot A23 of the processor, replaced Q4, 2N3669, 3/17/19

B131 Adder in slot A21 of the processor, replaced Q1, Fairchild 2N3009, 7/24/21

B169 Inverter (Multiplexor) in slot B26 of the processor with a spare, 3/30/19

B169 Inverter (Multiplexor) in slot B31 of the processor with a spare, 12/8/20

B310 Delay Line in slot EF29 of the processor with a spare, 5/11/13

B310 Delay Line in slot EF29 of the processor with a repaired module, 6/15/13

B213 JAM Flip-Flop in slot H33 of the processor with a spare, 2/2/13

B213 JAM Flip-Flop in slot C39 of the processor with a spare, 3/23/19

B213 JAM Flip-Flop in slot C18 of the processor with a spare, 6/29/13

B213 JAM Flip-Flop in slot C35 of the processor with a spare, 10/5/13

B213 JAM Flip-Flop in slot C35 of the processor with a spare, 10/14/13

B213 JAM Flip-Flop in slot D20 of the processor with a spare, 6/22/13

B213 JAM Flip-Flop in slot D21 of the processor with a spare, 4/13/19

B213 JAM Flip-Flop in slot D27 of the processor with a spare

B213 JAM Flip-Flop in slot D28 of the processor with a spare, 3/16/13

B213 JAM Flip-Flop in slot H33 of the processor with a spare, 2/2/13

B213 JAM Flip-Flop in slot E20 of the I/O controller with a spare, 8/31/13

B213 JAM Flip-Flop in slot A16 of the Memory controller with a spare 7/29/23

B310 Delay Line in slot EF29 of the processor with a spare, 5/11/13

B301 Delay Line in slot H22 with a spare, 10/5/22

B310 Delay Line in slot EF36 of the Core Memory with a spare, put the original repaired board back 8/10/19

B360 Adjustable Delay Line in slot D33 of the Core Memory with a spare, 7/6/13

G009 Sense Amplifier in slot C25 of the Core Memory with a spare, 2/16/20

G009 Sense Amplifier in slot B24 of the Core Memory with a spare, 8/30/23

G009 Sense Amplifier in slot B25 of the Core Memory with a spare, 8/30/23

G219 Memory Selector in slot AB09 of the Core Memory with a spare, 2/2/13

G219 Memory Selector in slot HJ24 of the Core Memory with a spare, 2/16/13

G219