TD8E Simple Dectape Controller SDLD C0 Glitch

The DEC TD8E Simple Dectape Controller has a design issue that causes a significant glitch on the C0 signal on the Omnibus when the SDLD IOT instruction is executed. The C0 glitch is large enough in some systems with long Omnibus backplanes to cause the AC to be cleared when it should not be.

The image above shows the part of the TD8E logic that decodes the IOT instructions when this TD8E is addressed.

When this TD8E is address IC E26 drives the CC 67 X L signal low.

IC E45 is a Signetics 8251 BCD to Decimal Decoder which is enabled when the CC 67 X L signal drives the "D" input on pin 2 low.

The MD 09, MD 10, and MD 11 signals from the Omnibus encode only eight possible IOT instructions, so the 8 & 9 outputs from the 8251 are not used.

The case that we are interested in is the SDLD IOT instruction 6775.

When the SDLD IOT instruction is executed, IC E45 will decode the 5 on the MD 09, MD 10, and MD 11 signals and drive the "5" output on pin 3 low.

It looks like it takes the 8251 about 20 ns to decode the inputs and drive one of the outputs low.

The SDLC, SDRC, SDRD, and SDLD IOT instructions read/write data from/to the TD8E so the C0 and C1 are driven to clear (or not) the AC, and set the data direction on the Omnibus.

The IC E33 is a Signetics N8881N and drives both the C0 and the C1 signals on the Omnibus.

Pins 2 & 11 of E33 are driven high by pin 2 of E44 when a SDLC, SDRC, SDRD, or SDLD IOT instruction is being executed and enables the output of E33.

If the C0 signal on the Omnibus is driven low the AC will be cleared when the IOT instruction is executed.

This is the desired behavior for the SDLC, SDRC, and SDRD IOT instructions, but not for the SDLD IOT instruction.

When the SDLD IOT instruction is executed the "5" output on pin 3 of E33 will drive pin 12 of E33 low, which will disable the output drive from E33.

Unfortunately the Signetics 8251 takes 20 ns to decode the MD 09, MD 10, and MD 11 signals and drive the "5" output on pin 3 low.

This means that E33 will drive the C0 Omnibus signal low until it it is disabled.

This is referred to as the C0 glitch.

Click on the image for a larger view.

The upper trace is pin 11 on E33 (CC AND 09 H) and the lower trace is pin 12 on E33 (- CC SDLD H).

IC E33 pin 12 was driven low by the 8251 E45 about 20 ns after pin 11 was driven high by the SP380N E44.

Click on the image for a larger view.

The upper trace is pin 11 on E33 (CC AND 09 H) and the lower trace is pin 13 on E33 (C0).

IC E33 pin 12 was low about 20 ns after pin 11 was driven high, but it takes about 100 ns for the Omnibus C0 signal to get back above the 2V threshold.

Click on the image for a larger view.

This is the same image as above, but with a compressed horizontal scale.

The M8320 Bus Loads (terminator) board has 1.5 kOhm resistors (R93 & R94) between +15V and C00 (pin CE1) and C01 (Pin CH1).

The D664 (1N3606) clamping diodes (D135 & D137) go to ground to limit the undershoot to about 0.6V.

The D664 (1N3606) clamping diodes (D136 & D138) go to a power bus that has a 1.5 kOhm resistor (R76) to +15V and is connected to four D662 (1N645) diodes (D141-D144) to ground.

It looks like the idle