DEC VAX 8600 in Lucite
The VAX 8600, code-named "Venus", was introduced in October 1984 as the successor of the VAX-11/785.
The VAX 8600 CPU had an 80 ns cycle time (12.5 MHz) and was implemented with Emitter Coupled Logic (ECL) macrocell arrays (MCAs). The CPU consisted of four major logical sections, the E Box, F Box, I Box and M Box. The E Box executed all instructions and had an arithmetic logic unit (ALU) and barrel shifter. The F Box, or floating point accelerator (FPA), was an optional feature that accelerates floating-point instructions as well as integer multiplication and division. The I Box fetches and decodes instructions. The M Box controls the memory and I/O, translates virtual addresses to physical addresses and contains a 16 KB data cache.
The CPU used 145 MCAs. These were large scale integration devices fabricated by Motorola in their 3 µm MOSAIC bipolar process. They were packaged in 68-pin leadless chip carriers or pin grid arrays and were mounted onto the printed circuit board in sockets or were soldered in place. An additional 1,100 small scale integration (SSI) and medium scale integration (MSI) ECL logic devices were used. These ICs were spread out over 17 modules plugged into a backplane.
The VAX 8600 supports up to 256 MB of ECC memory and has eight slots on the backplane for memory modules. The system originally used 4 MB memory mo