Commodore SX-64 Portable Computer Restoration
The computer powers on, the diskette LED goes on for a few seconds, and the screen shows a color background. without a border or text. Pressing the diskette reset button causes the diskette LED to go on for a few seconds. There is no diskette seek activity. The diskette controller has its own 6502 CPU, and will turn on the spindle motor for a few seconds, but won't seek until the main CPU dells it to do something.
We looked at the J19 Serial Bus Cable (IEEE-488) signals for the floppy diskette controller. The clock and data signals are always low. We disconnected the cable between the FDC board and the I/O board, and the serial data signals went to 5V. So it looks like CIA #2 on the I/O board is holding the diskette controller CLK and DATA signals low.
We looked at the input and output clock signals for the CPU chip. All look OK and are 1 MHz.
We looked at the data signals on the CPU. We can see tri-state activity on all 8x data lines, so the CPU is running something.
We grounded the reset pin on the CPU chip so we could trigger the 'scope when the data activity started. We were surprised to see that the CPU reset and started again instead of halting when the reset line was held low. According to the 6510 datasheet this is not the right behavior. We will try swapping the CPU chip with a known good one.
Next week we will connect a logic analyzer to the CPU chip and capture the data being fetched from the Kernel EPROM. We can compare it to the disassembled listing of the Kernel EPROM to make sure that the data is OK. We will also make a new Kernel EPROM just in case this one is bad.
We took apart a working C64 to see if could use it to test the 6510 CPU and the PLA chip to test the SX-64. We were a little disappointed to find that the only socketed chip in the C64 is the SID.
We started looking at the CPU signals again. We can trigger the 'scope in the rising edge of the RES signal to the CPU. We don't see reasonable values on the data or address lines. We will try more signals with the logic analyzer on Saturday.
We read the Kernel EPROM with a programmer and compared it to a binary image of what is supposed to be in the EPROM. It checked out OK. That was disappointing because it is a common failure and would have been easy to fix.
The 14.3, 8.18, and 1.02 MHz clocks from the Clock Unit all look great.
We added a push-button to the CPU board so we could trigger the 'scope on the RST\ signal.
After RST\ goes inactive we should see 6x clock pulses, and then the address and data activity described below. Unfortunately the address and data activity is completely random after a reset. This is looking like a failed 6510 CPU chip. We will look in some early C64 machines to see if we can find a socketed 6510 to try in the SX-64.
Notes for next time:
Trigger the 'scope on the CS\ signal for the Kernal EPROM and look at the data lines. We should see data on all lines when CS\ is low.
Strobe the logic analyzer on the CS\ signal for the Kernal EPROM.
We should see:
After RES\ goes high
Address 0xFFFC accessed and 0xE2 & 0xFC read from the Kernal EPROM
Address 0xFCE2 accessed and 0xA2, FF, 78, 9A, D8, 20, 02, FD read from the Kernal EPROM
Address 0xFD02 accessed and 0xA2, 05, BD, 0F, FD, DD, 03, 80, D0, 03 read from the Kernal EPROM
Address 0xFCEA accessed and 0xD0, 03 read from the Kernal EPROM
Address 0xFCEF accessed and 0x8E, 16, D0, 20, A3, FD read from the Kernal EPROM
The pinout on the internal serial cables is different from the external connector. We spent the time to determine the internal connector pinout on the FDC board.
DIN serial connector on the back of the chassis
1 Serial Service Request
3 Serial Attention
4 Serial Clock
5 Serial Data
6 Serial Reset
6-Pin connector on FDC Card, and I/O Card
1 Serial Reset
2 Serial Data
3 Serial Clock
4 Serial Attention
6 Serial Service Request