Intel Intellec MDS-800 #1

MDS-800 Front Panel Controller

A cable plugs onto the I/O connector on the top of the board and connects to the front panel of the chassis. This provides the connection to the Interrupt, Boot, and Reset switches and LEDs on the front of the chassis. The 256 Byte 1702A EPROM on this board contains the system bootstrap code. When the Boot switch is on, the EPROM occupies the memory addresses 0000h-00FFh, and drives the INH1 signal on the Multibus to prevent RAM boards and INH2 to prevent ROM boards from responding to those addresses. This board also contains the parallel priority resolution circuitry that allows for multiple masters on the Multibus backplane. The diskette controller uses this circuit to kick the CPU off the Multibus and allow the for DMA between RAM and the diskette controller. There is a real-time clock circuit on this board that generates an interrupt at a 1 mS rate. There is also a circuit that can prevent the system from hanging if you access a nonexistent memory or I/O address.

MDS-800 CPU Module, PWA 1000340-01E

This board holds the 2 MHz 8080A CPU, 4x 8212 buffers, and a 3214 interrupt controller.

MDS-800 DRAM Module #1

This board holds 32x Intel 2107C-1 4 kb (4096 x 1) 150 nS DRAMS in 4x banks of 4kB x 8 for a total of 16 kB x 8 of RAM. It has an onboard DRAM controller that handles the memory refresh cycles without needing the CPU. This board occupies the memory addresses 0000h-3FFFh. Two of these boards can be paired to provide 16k x 16 of RAM.

MDS-800 DRAM Module #2

This board holds 16x Intel 2117-3 16 Kb (16384 x 1) 300 nS DRAMS, and 16x Intel 2109-3 8 Kb 8 Kb (8192 x 1) 300 nS DRAMS for a total of 48 KB of RAM. It has an onboard DRAM controller that handles the memory refresh cycles without needing the CPU. This board occupies the memory addresses 4000h-FFFFh.

MDS-800 Double-Density Diskette Controller Channel Module

This board has a bit-slice processor that reads the I/O Parameter Block from RAM, interprets the command in the IOPB, controls the diskette drive through the Diskette Interface board, and DMAs the data between RAM and the diskette drive. The switch at the bottom right sets this board to the default I/O address of 78h. The 8-bit CPU on this board is made from 4x Intel 3002 2-bit Central Processing Elements, an Intel 3001 Microprogram Control Unit, and 512 x 32 of Microprogram stored in 4x Intel 3604 PROMs.

MDS-800 Double-Density Diskette Interface Module

This board holds all of the buffer logic to connect the Channel board to the diskette drive. It also has the logic for the Multibus priority circuit. This is the board version for Shugart diskette drives. There is a different board for CDC diskette drives.

MDS-800 Monitor Module

This board provides the serial ports for the CRT (up to 4800 baud) and the 20 mA TTY & paper tape reader (110 baud), implemented with the two chips at the top right that are Intel 8251 USARTs. It also implements parallel interfaces for the 200 CPS paper tape reader and 75 CPS punch, line printer, and PROM programmer.

The large chip at the left is an Intel 8316A 2048 x 8 ROM that holds the MDS Monitor. A second 8316 ROM could be installed to provide 2048 x 16 of code for a 16-bit CPU. The Monitor ROM occupies the memory addresses F800h-FFFFh