Intel MDS-II Model 230 Development System Restoration

10/9/21

We disassembled the system to inspect it and to take pictures of everything.

We disconnected the DC outputs that connect the power supply to the Multibus backplane and to the I/O controller board on the back of the chassis. We plugged the AC power cord into a Variac, set the Variac for a low voltage output, and turned on the power. Unfortunately nothing happened. We are in the process of determining why the AC power isn't getting to the fans and power supply.

With the Variac set to 30 VAC output we see 30 VAC on the internal floppy power cable. That should mean that the power cord, fuse, voltage selection switch, and power switch are all OK. We checked the resistance of the thermal cutout. It was just a few ohms, so that is OK.

We reassembled the chassis, reconnected all of the internal DC power cables, and powered up the system with 30 VAC input. This time the fans started running slowly, so there was AC power to the power supply. We slowly increased the AC voltage and the DC voltages to the backplane all look OK.

We plugged all of the boards into the chassis and powered it up. The LEDs for switches 0, 1, and 2 and RUN lit. Nothing was displayed on the CRT. We fiddled with the brightness control and could sometimes see a pattern on the CRT while the control was moved.

We set the LOCAL/LINE/DIAGNOSTIC switch on the back to diagnostic, and after a few minutes the CRT displayed INTELLEC SERIES II IOC DIAGNOSTIC V1.1. We ran the GENERAL and KEYBOARD/CRT diagnostics and the passed. We did not run the DISK diagnostics because this system does not have an internal floppy diskette drive.

With the LOCAL/LINE/DIAGNOSTIC switch set to LOCAL everything we type on the keyboard is displayed on the CRT.

With the LOCAL/LINE/DIAGNOSTIC switch set to LINE and reset the system. The CRT displayed SERIES II MONITOR, V1.2 and a prompt. We tried a few commands and it looks like it is working.

10/13/21

We connected the diskette chassis from the MDS-800 to the MDS-II, put a CP/M diskette in drive 0, and pushed the reset button. It cleared the screen and displayed the monitor prompt on the CRT. We tried ISIS V3.4 and ISIS 4.1 and got the same results. Maybe the boot sequence for the MDS-II is different from the MDS-800? Time to read the manuals.

The MDS Monitor doesn't display on the CRT anymore. We removed all of the boards but the IPB, and still no monitor prompt. We reseated all of the chips on the IPB and no change. Maybe the IPB CPU board (most likely) or the IOC I/O Controller board (less likely) is not working correctly.

The power supply voltages to the Multibus chassis are all OK.

10/20/21

We bought some 327 light bulbs on eBay so now the power switch lights up.

We had several suggestions that the Boot and Monitor EPROMs might have lost their contents. We made new 2716 EPROMs with the same revision level EPROMs, but it didn't change the behavior.

We read through the Hardware Reference manual for this system. It is very detailed and has a good explanation of the boot sequence. After a RESET the 8080 CPU starts executing instructions at address 0x0000. The Boot EPROM at this point is at address 0x0000 and has a JMP 0xE806 as the first instruction. After this instruction is executed the Boot EPROM address is changed to 0xE800 and the 8080 CPU continues executing code at address 0xE806. The 8080 CPU disabled Interrupts, configures the interrupt controllers, RAM, and Serial Ports, and then tried to boot from diskette.

We connected the 'scope to the CS signals on pin 20 of the Boot and Monitor EPROMs. We see a sequence of 8 fetches from the BOOT EPROM at 3 uS intervals and a 2 uS pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, and then a 200 nS CS, and then CS for the Boot EPROM goes high. We don't see any CS activity for the Monitor EPROM.

Looking at the source code listing of the Boot EPROM we see the instruction sequence JMP 0xE806, DI, MVI A 0x02, OUT 0xFF that need 8 fetches and then the OUT instruction causes the 2 uS pause. Then 4x MVI A and OUT for a total of 4x fetches each and another OUT for a total of 2x fetches. Then MVI A and OUT for a total of 4x fetches each and another OUT for a total of 2x fetches. Then a sequence of 3x MVI A and OUT for a total of 4x fetches each. and another OUT for a total of 2x fetches. This shows that most of the initialization code is running, but something breaks when it is configuring the RTC.

We added the START UP/ signal from IC A73 pin 10 and the SEL BOOT/ signals from IC A73 pin 7 to the 'scope.

The 8080 CPU is executing 5x fetch cycles and then START UP/ goes inactive switching the BOOT EPROM's address from 0x0000 to 0xE800. The 8080 is executing a JMP 0xE806 from the BOOT EPROM starting at address 0x0000, then a DI, then the MVI and START UP/ goes inactive so that the data of the MVI comes from 0xE808 not from 0x0008. It would seem that the START UP/ signal would go inactive after the OUT 0xFF instruction, and not earlier.

Time to look at the data bits.

The data from the Boot EPROM is:

• C3, 06, E8, that is the JMP 0xE806

10/23/20

We updated the firmware in our Rigol 'scope, ran the full 'scope recalibrate cycle, and recalibrated the logic analyzer. Everything worked, so hopefully we can capture better data about the 8080 boot sequence.

10/23/21

We looked at the MEMR signal with channel 1 and the pins on the BOOT EPROM with the logic analyzer. When the OUT instruction is executed we see linearly descending signal on several of the data pins. We eventually determined that the the EPROM outputs are turned off at this time so it doesn't matter. We moved the logic analyzer probes to the data buffers A84 & A85 and get better results. We can also see the data written to the I/O ports with this configuration.

The Logic Analyzer broke again. A Logic Analyzer recalibrate failed. Channel 3 and Channel 5 don't work. We recalibrated the 'scope and the Logic Analyzer recalibrated. We will try again. Oops, Channel 5 is not working again. We will clean all of the connectors and try again.

After reset the bytes on the data bus are:

• 0000, C306E8: JMP E806

• E806, F3: DI

• E807, 3E02: MVI A, 02

• xxxxx

• E82B, 3EB6: MVI A, B6

• E82D, D3F3, OUT F3

• E82F, 21CD04, LXI, H 04CD

We got all the way through the code up to where we start to initialize the RTC for 1 mS. At 0xE82D it wrote 0xB6 to the ITCP (Interval Timer Output Command Port) port at 0xF3. Then it fetched two bytes of the LXI H, RTCC and it hung with the MRDC signal active and the data lines all high (zeros).

I can see activity where the MRDC signal goes inactive every ms to it looks like maybe the RTC is affecting the CPU. There is no activity on the RTC signal from the 8253 chip, so we will need to go exploring. After about 5 seconds the CPU goes back to running full speed and is executing a loop with an I/O instruction in it. next time we can connect the logic analyzer to the address lines and see where it is going.

10/27/21

For the 'scope image above, we connected 'scope channel 1 to the INH2/ signal on pin 11 of IC A6, this is the CS signal for the Boot and Monitor EPROMs. We can see the INH2/ signal go active every time the 8080 CPU fetches a byte from the Boot EPROM. At 190 us after RESET signal goes inactive the INH2/ activity stops.

We connected 'scope channel 2 to IC A6 pin 15, this is the SEL BOOT/ signal that enables the Boot EPROM. We see the SEL BOOT/ signal active until 190 us after RESET goes inactive and then the SEL BOOT/ signal goes high.

We connected 'scope channel 3 to pin 7 of IC A56, this is the STSTB signal. We can see 50 ns low pulses on the STSTB signal every 3 us or 3.5 us after the the INH2/ activity starts and then the pulses stop. After about 800 us we see a single negative pulse, and then every 1 ms thereafter.

We connected 'scope channel 4 to pin 5 of IC A56, this is the SYNC signal from the 8080A CPU. This is also the XSTR Transfer Start Request signal. We can see 400 ns positive pulse every 3 us or 3.5 us after RESET goes inactive and then the pulses stop after aboit 190 us. After about 800 us we see a single positive pulse, and then every 1 ms thereafter. This pulse is centered on the STSTB pulse.

We also looked at the RESET signal. It goes inactive at the beginning and does not go active again.

The RDYIN and READY both stop 190 us after RESET goes inactive.

The XACK/ signal pulses stop 190 us after RESET goes inactive. This signal can also come from the TO ACK, RAM ACK, and LOC ACK signals.

The LOC ACK signal has 900 ns positive pulses that stop about 190 us after RESET goes inactive.

The RAM AACK signal is always high.

The INTA signal is always high.

The CLR/ signal on pin 15 of the 74LS259 A73 goes high after RESET goes inactive and stays high.

The G/ input on pin 14 of IC A73 goes low after RESET goes inactive and stays low.

We connected the dual-diskette chassis to the MDS-800 that we know works OK, inserted a CP/M 2.2 diskette into drive 0, and were able to get it to boot! So we now know that the right diskette drive works OK. We tried to list the directory of the left diskette, and ISIS said that the drive was not ready. Something to check on Saturday.

We tried to boot CP/M on the MDS-II. It selected the drive, but did not boot. We can swap the diskette controller from the MDS-800 into the MDS-II to see if that is the problem.

11/6/21

We tried the iPSC-202 Diskette Interface and Channel boards, one at a time, in the MDS-800 system. The MDS-800 will boot CP/M from drive-0 in the MDS-II diskette chassis. It will not boot with the Interface board or the Channel board from the MDS-II installed.

It looks like the diskette controller boards and switch settings are different between the two systems. The MDS-800 has a 1001036-04 Revision R Interface board, and the MDS-II has a 101036-02 Revision E. The Priority selector switch was set to 3 on both boards. The MDS-800 has a 1000467-04 Revision L Channel board, and the MDS-II has a 1000467-02 Revision L. Both boards have the switch set to On, On, On, Off, Off, Off, Off, On to set the I/O address to 0x78.

We cleaned the gold fingers on both boards from the MDS-II, fiddled with the switches, and reseated the ICs. If the Channel board from the MDS-II is installed in the MDS-800 it will not boot, and sometimes will not run the monitor. The Interface board from the MDS-II seems to work OK in the MDS-800. After reseating the ICs several times, and reseating the boards in the chassis several times, when both boards from the MDS-II were installed in the MDS-800 it booted both CP/M and ISIS.

The case was broken at the lower left and the top right of the CRT. A little JB weld fixed that.

11/10/21

We replaced IC A54, a 7432, that we temporarily installed when we fixed the IPB board with the correct 74S32 IC. The "S" in the part number means that the IC is made with Schottky technology and is faster than an normal TTL IC.

We looked at the index pulse width from the right diskette drive. It was about 1.1 us, and should be 1.2-2.4 ms. We split the difference an set it to 1.7 ms. The system will not boot from the diskette now. We set the index pulse back to where it was and it will still not boot. We tried the other diskette chassis and it would not boot.

So, it looks like the diskette controller is misbehaving again. We reseated the controller boards and cables, but there was no improvement. We will work on this issue on Saturday.

11/13/21

We decided to fix the diskette chassis from the MDS-II using the MDS-800 because the diskette controller in the MDS-800 works reliably. The first project is to adjust the index pulse for the right drive to 1.7 ms duration. The second project is to determine why the left drive does not go ready. This is likely an index pulse that is too short and can be adjusted.

We readjusted the right drive index to 1.7 ms, split between the minimum of 1.2 ms and maximum of 2.2 ms. The MDS-800 booted ISIS-II from this drive. We looked at the index pulse on Test Point 12 of the left drive. There was no pulse. We looked at the signal from the index sensor on pin 4 of IC 1G. The signal was trapezoidal and we adjusted the peak to about 1.7 ms duration. There is a 2V reference signal on pin 5 of IC 1G. Now there is an index pulse signal on pin 2 of IC 1G, and also on Test Point 12. We adjusted the index pulse width to about 1.7 ms.

It looks like the connector J2 where all of the signals connect to the controller board on the bottom of the diskette drive is intermittent. Time for some cleaning. We sprayed the connector with some DeoxIT, and it is not intermittent any more. Now both diskette drives go ready.

We booted ISIS 4.1 from the right drive, put a SSSD diskette in the left drive, and executed the "IDISK :F1:TEST" command to reformat a diskette in the left drive. After a while it displayed ERROR 24 USER PC 39BA, FDCC= 20, DRIVE 1. We tried the MDS-800 diskette chassis and had the same results. We tried another diskette and that worked OK. We switched back to the MDS-II diskette chassis, and both drives work OK. We were able to format and copy diskettes using ISIS 4.1 and CP/M 2.2, so we declared success.

We will look at the iSCB-202 double-density diskette controller during the next repair session.

11/17/21

We applied DeoxIT to the chip sockets and gold fingers on the two boards that make up the iSBC-202 diskette controller. After the treatment the system booted CP/M and ISIS-II from diskettes.

We tried to use the IMG2MDS program to write an image of a diskette to a physical diskette. To do this we needed to disconnect the keyboard and use the serial console port #2. Serial console CH 1 works, but CH 2 does not. The program that is supposed to change the serial console baud rate from 2400 to 19,200 only works with serial console CH 1, so we need to fix that before we can write images to diskettes.

11/20/21

We opened the MDS-II chassis so we could see how serial port CH 2 is jumpered. All of the jumpers are at the factory settings.

Serial Ch 2 has RxD & Txd swapped and RTS & CTS looped, so we need to swap pins 2 & 3 and loop pins when connected and to a PC serial port. We reset the MDS, hit the space bar on the PC, and the MDS monitor prompt showed up on the CRT, not on the PC.

We directly connected the PC's serial port to MDS CH1. We reset the MDS, hit the space bar on the PC, and the MDS monitor prompt showed up on the PC. Unfortunately we need to use MDS CH 2 for the IMG2MDS program.

11/21/21

The MDS experts think that there might be a software bug in the V1.2 MDS monitor. We will program another 2708 EPROM containing the V1.3 MDS monitor and give it a try.

11/24/21

We downloaded the V1.3 Monitor files from Bill Beech's WWW site. Unfortunately none of the files in the collection are suitable for sending to an EPROM programmer, and the file names for the Boot/Diag and the Monitor EPROMs are swapped. The monIIv13.rom file contained both the Boot/Diag and the Monitor EPROM images. We used Hexedit to split the combined EPROM image into two 2716 EPROM images, and converted the individual files into Intel hex files suitable for sending to the EPROM programmer. The MDS-II booted with the new EPROMs installed, but complained that the EPROM checksums are incorrect. The source code has an added byte at the end of the EPROM image to make the checksum correct. The two added bytes must have been modified in the combined EPROM image, so are incorrect in the split EPROM image files. It works OK, but the error message is annoying. We need to reprogram the EPROMs with a modified image that has the correct checksum byte. We will do that on Saturday.

11/27/21

We found the byte in the Boot/Diag and the Monitor EPROM that adjusts the checksum to be the right value. We recalculated the checksum adjustment bytes, modified the EPROM image files, and programmed new Boot/Diag and Monitor EPROMs.

We connected a serial terminal emulator to the CH 1 serial output and disconnected the keyboard. After entering two spaces the V1.3 Monitor prompt was displayed. The serial terminal also worked when connected to CH 2 with a null-modem cable, so the V1.3 Monitor fixed the problem that we had with the V1.2 Monitor.

The diskettes have been a little flaky in this system. We used DeoxIT on the chip sockets and connetors on the controller boards. That helped, but it would stop working after a while. We used DeoxIT on the cable between the MDS-II chassis and the diskette chassis and it seems better now.

Now we can go back to trying to write diskette images using the MDS-II and the IMG2MDS program.

It booted CP/M on the first try, so the DeoxIT treatment seems to have made it more reliable. Well, that didn't last. It is back to being flaky again.

To Do:

Use Martyn Vale's IMG2MDS tool to create diskette images.

Fix the left diskette drive. 11/13/21 Done

Start working on the LSI dot-matrix printer that came with this system.

Fix the IPB board. 10/27/21 Done!

See if there are newer Boot/Diagnostic and Monitor EPROM images available. Make V1.3 EPROMs. 11/27/21 Done!

Power up the diskette chassis. If that works, connect it to the MDS-II chassis with a floppy cable and try to boot ISIS and CP/M from diskette. We still need to test the serial ports, connect the printer and see if that works, make a cable for the paper tape reader and see if that works. The last project will be to removed the math board, install the ICE-85 boards, connect the pod to an MCS-85 and see if we can do hardware debugging.

We also need to get the interface cables from the donor. Done!