Intel MDS-II Model 230 Development System Restoration
We disassembled the system to inspect it and to take pictures of everything.
We disconnected the DC outputs that connect the power supply to the Multibus backplane and to the I/O controller board on the back of the chassis. We plugged the AC power cord into a Variac, set the Variac for a low voltage output, and turned on the power. Unfortunately nothing happened. We are in the process of determining why the AC power isn't getting to the fans and power supply.
With the Variac set to 30 VAC output we see 30 VAC on the internal floppy power cable. That should mean that the power cord, fuse, voltage selection switch, and power switch are all OK. We checked the resistance of the thermal cutout. It was just a few ohms, so that is OK.
We reassembled the chassis, reconnected all of the internal DC power cables, and powered up the system with 30 VAC input. This time the fans started running slowly, so there was AC power to the power supply. We slowly increased the AC voltage and the DC voltages to the backplane all look OK.
We plugged all of the boards into the chassis and powered it up. The LEDs for switches 0, 1, and 2 and RUN lit. Nothing was displayed on the CRT. We fiddled with the brightness control and could sometimes see a pattern on the CRT while the control was moved.
We set the LOCAL/LINE/DIAGNOSTIC switch on the back to diagnostic, and after a few minutes the CRT displayed INTELLEC SERIES II IOC DIAGNOSTIC V1.1. We ran the GENERAL and KEYBOARD/CRT diagnostics and the passed. We did not run the DISK diagnostics because this system does not have an internal floppy diskette drive.
With the LOCAL/LINE/DIAGNOSTIC switch set to LOCAL everything we type on the keyboard is displayed on the CRT.
With the LOCAL/LINE/DIAGNOSTIC switch set to LINE and reset the system. The CRT displayed SERIES II MONITOR, V1.2 and a prompt. We tried a few commands and it looks like it is working.
We connected the diskette chassis from the MDS-800 to the MDS-II, put a CP/M diskette in drive 0, and pushed the reset button. It cleared the screen and displayed the monitor prompt on the CRT. We tried ISIS V3.4 and ISIS 4.1 and got the same results. Maybe the boot sequence for the MDS-II is different from the MDS-800? Time to read the manuals.
The MDS Monitor doesn't display on the CRT anymore. We removed all of the boards but the IPB, and still no monitor prompt. We reseated all of the chips on the IPB and no change. Maybe the IPB CPU board (most likely) or the IOC I/O Controller board (less likely) is not working correctly.
The power supply voltages to the Multibus chassis are all OK.
We noticed that IC A27, and Intel B3222 DRAM Refresh Controller, on the IPB has a corner broken out of the chip. Hopefully the chip is still functional.
We looked at the signals on the B3222 chip. After power up Pin 3, CYREQ, has 400 nS negative going pulses every every 2 uS. The RUN LED is on bright at this time. Pin 4, STARTCY, has 100 nS negative going pulses every 15 uS after power up. Pin 18, BUSY, has 600 nS negative going pulses every 15 uS. Pin 19, REFON, has 800 nS negative going pulses every 15 uS.
After a while, or after a reset the RUN LED is dim and there are no pulses on pin 3, but the other three signals on the B3222 are active but have a 15 uS period. After another reset or power cycle there are no signals on pin 3, but periodically there is a flicker of activity.
This behavior looks OK, but the lack of a CYREQ signal is concerning.
The image on the right shows the signals on IC A31, a 74ls155 decoder. It is used to generate the DRAM refresh CYREQ signal based on the bus address being in the RAM address range, either the MRDC/ or the MWTC/ signal being active and the INH1/ signal being inactive. The yellow signal is pin 1, DATA1, cyan is pin 2, STB 2, magenta is pin 3, SEL B, and blue is pin 5, 1Y2.
In this 'scope image we don't see any activity on pin 5, MEMR/ so it will not create a CYREQ signal. We see lots or RAM address decodes on pin 1, but not coincident with a MRDC/ in pin 2 and and INH1/ signal on pin 3. After a power cycle we see one MEMR/ cycle, shown below for 4 ms a few seconds after a reset.
In this case pin 1 went high when the RAM address range was selected, Pin 2 was MRDC/ going low because a memory read was active, pin 3 was high because INH1/ was inactive, and the result was pin 5 MEMR/ went low to generate a CYREQ signal. This correct signal sequence was rare and hard to trap.
We need to chase the signals further upstream to determine why we are not seeing the correct sequence of signals. The leading edge of the INH1/ signal has a slow rise time that could indicate a damaged driver chip.
We bought some 327 light bulbs on eBay so now the power switch lights up.
We had several suggestions that the Boot and Monitor EPROMs might have lost their contents. We made new 2716 EPROMs with the same revision level EPROMs, but it didn't change the behavior.
We read through the Hardware Reference manual for this system. It is very detailed and has a good explanation of the boot sequence. After a RESET the 8080 CPU starts executing instructions at address 0x0000. The Boot EPROM at this point is at address 0x0000 and has a JMP 0xE806 as the first instruction. After this instruction is executed the Boot EPROM address is changed to 0xE800 and the 8080 CPU continues executing code at address 0xE806. The 8080 CPU disabled Interrupts, configures the interrupt controllers, RAM, and Serial Ports, and then tried to boot from diskette.
We connected the 'scope to the CS signals on pin 20 of the Boot and Monitor EPROMs. We see a sequence of 8 fetches from the BOOT EPROM at 3 uS intervals and a 2 uS pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 4 fetches and a pause, 2 fetches and a pause, and then a 200 nS CS, and then CS for the Boot EPROM goes high. We don't see any CS activity for the Monitor EPROM.
Looking at the source code listing of the Boot EPROM we see the instruction sequence JMP 0xE806, DI, MVI A 0x02, OUT 0xFF that need 8 fetches and then the OUT instruction causes the 2 uS pause. Then 4x MVI A and OUT for a total of 4x fetches each and another OUT for a total of 2x fetches. Then MVI A and OUT for a total of 4x fetches each and another OUT for a total of 2x fetches. Then a sequence of 3x MVI A and OUT for a total of 4x fetches each. and another OUT for a total of 2x fetches. This shows that most of the initialization code is running, but something breaks when it is configuring the RTC.
We added the START UP/ signal from IC A73 pin 10 and the SEL BOOT/ signals from IC A73 pin 7 to the 'scope.
Chanel 1 is the CS signal on pin 20 of IC A57 the Boot EEPROM, channel 2 is the CS signal on pin 20 of IC A48 the Monitor EPROM, channel 3 is the START UP/ signal on pin 10 of IC A73, and channel 4 is the SEL BOOT signal on pin 7 of IC A73.
I expected to see the START UP/ signal go inactive after the three fetches for the JMP 0xE806. This is when the address of the BOOT EPROM is changed from 0x0000 to 0xE800. I didn't expect to see the START UP/ signal go active again.
I expected the SEL BOOT/ signal to inactive after the boot code failed to boot from the diskette and then it jumped into the Monitor EEPROM. This happened before the initialization code was finished so it deactivated the BOOT EPROM and therefore we didn't see any more CS signals.
Something is really broken here. Time to figure out what it was doing when the START UP/ signal went active when it should not have.
The 8080 CPU is executing 5x fetch cycles and then START UP/ goes inactive switching the BOOT EPROM's address from 0x0000 to 0xE800. The 8080 is executing a JMP 0xE806 from the BOOT EPROM starting at address 0x0000, then a DI, then the MVI and START UP/ goes inactive so that the data of the MVI comes from 0xE808 not from 0x0008. It would seem that the START UP/ signal would go inactive after the OUT 0xFF instruction, and not earlier.
Time to look at the data bits.
The data from the Boot EPROM is:
C3, 06, E8, that is the JMP 0xE806
We updated the firmware in our Rigol 'scope, ran the full 'scope recalibrate cycle, and recalibrated the logic analyzer. Everything worked, so hopefully we can capture better data about the 8080 boot sequence.
We looked at the MEMR signal with channel 1 and the pins on the BOOT EPROM with the logic analyzer. When the OUT instruction is executed we see linearly descending signal on several of the data pins. We eventually determined that the the EPROM outputs are turned off at this time so it doesn't matter. We moved the logic analyzer probes to the data buffers A84 & A85 and get better results. We can also see the data written to the I/O ports with this configuration.
The Logic Analyzer broke again. A Logic Analyzer recalibrate failed. Channel 3 and Channel 5 don't work. We recalibrated the 'scope and the Logic Analyzer recalibrated. We will try again. Oops, Channel 5 is not working again. We will clean all of the connectors and try again.
After reset the bytes on the data bus are:
0000, C306E8: JMP E806
E806, F3: DI
E807, 3E02: MVI A, 02
E82B, 3EB6: MVI A, B6
E82D, D3F3, OUT F3
E82F, 21CD04, LXI, H 04CD
We got all the way through the code up to where we start to initialize the RTC for 1 mS. At 0xE82D it wrote 0xB6 to the ITCP (Interval Timer Output Command Port) port at 0xF3. Then it fetched two bytes of the LXI H, RTCC and it hung with the MRDC signal active and the data lines all high (zeros).
I can see activity where the MRDC signal goes inactive every ms to it looks like maybe the RTC is affecting the CPU. There is no activity on the RTC signal from the 8253 chip, so we will need to go exploring. After about 5 seconds the CPU goes back to running full speed and is executing a loop with an I/O instruction in it. next time we can connect the logic analyzer to the address lines and see where it is going.
For the 'scope image above, we connected 'scope channel 1 to the INH2/ signal on pin 11 of IC A6, this is the CS signal for the Boot and Monitor EPROMs. We can see the INH2/ signal go active every time the 8080 CPU fetches a byte from the Boot EPROM. At 190 us after RESET signal goes inactive the INH2/ activity stops.
We connected 'scope channel 2 to IC A6 pin 15, this is the SEL BOOT/ signal that enables the Boot EPROM. We see the SEL BOOT/ signal active until 190 us after RESET goes inactive and then the SEL BOOT/ signal goes high.
We connected 'scope channel 3 to pin 7 of IC A56, this is the STSTB signal. We can see 50 ns low pulses on the STSTB signal every 3 us or 3.5 us after the the INH2/ activity starts and then the pulses stop. After about 800 us we see a single negative pulse, and then every 1 ms thereafter.
We connected 'scope channel 4 to pin 5 of IC A56, this is the SYNC signal from the 8080A CPU. This is also the XSTR Transfer Start Request signal. We can see 400 ns positive pulse every 3 us or 3.5 us after RESET goes inactive and then the pulses stop after aboit 190 us. After about 800 us we see a single positive pulse, and then every 1 ms thereafter. This pulse is centered on the STSTB pulse.
We also looked at the RESET signal. It goes inactive at the beginning and does not go active again.
The RDYIN and READY both stop 190 us after RESET goes inactive.
The XACK/ signal pulses stop 190 us after RESET goes inactive. This signal can also come from the TO ACK, RAM ACK, and LOC ACK signals.
The LOC ACK signal has 900 ns positive pulses that stop about 190 us after RESET goes inactive.
The RAM AACK signal is always high.
The INTA signal is always high.
The CLR/ signal on pin 15 of the 74LS259 A73 goes high after RESET goes inactive and stays high.
The G/ input on pin 14 of IC A73 goes low after RESET goes inactive and stays low.
We looked at the cause of the SEL BOOT/ signal going high 190 us after reset. This will make the BOOT EPROM disappear and cause lots of problems when the CPU doesn't finish initializing the peripheral controller chips. The SEL BOOT/ signals comes from IC A73, a 74LS259 addressable latch. The G/ signal on IC A73 is strobed low to latch the data into the selected output pin. We observed that the G/ signal was always low, so whatever data happened to be on the DATA IN pin would get latched to the output pin selected by whatever signals happened to be on the A, B, and C pins address pins. It is likely that arbitrary data on the input and address pins just happens to select the pin Q3 output pin that makes the SEL BOOT/ signal and deactivated it.
The G/ signal comes from IC A54, a 74S32 a 2 Input Positive NOR Gate. This IC takes the IOWC/' and gates it with the SEL CPU/ to make the G/ signal.
In the 'scope image to the right Channel 1 is the CS signal for the Boot EPROM. It goes low each time a byte is read from the EPROM. After 8x low pulses there is a pause while the OUT instruction is executed. Channel 2 is the SEL CPU/ signal. It goes low each time an OUT 0xFF instruction is executed. Channel 3 is the IOWC/' signal, and channel 4 is the G/ signal. The G/ signal on channel 4 should be high except when both the SEL CPU/ and the IOWC/' signal are low. It is likely that this chip has failed so we ordered some new ones.
We looked at the SEL BOOT/ signal and the IOWC/ signal on pin 8, Enable on pin 1, and IOWC/' on pin 12 of IC A75 that gate the IOWC/ signal to make the IOWC/' signal. The IOWC/ signal goes low 2.5 us when the OUT instruction is executed. There is a 10 ns delay between IOWC/ and IOWC/'.
We looked at the IOWC/' signal on IC A47 pin 2, and it matches the signal on pin 12 of IC A75. We looked again at the IPWC/' signal on pin 2 of IC A54. In this case the signal on pin 2 of IC A54 matches the INIT/ signal, not the IOWC/' signal. This would let you read or write the CPUC latch, but it would probably work fine anyway.
We determines that IC A54 has failed so we removed it, installed a socket, and installed a 7432 that we had. We ordered some 74S32 parts from from Digikey and will replace the 7432 with a 74S32 when we get them. When we powered on the system we were rewarded with a SERIES II MONITOR, V1.2 prompt, so it looks like everything is working again.
We then entered the Z$ command. The enables the Boot/Diagnostic EPROM at 0xE800 and runs diagnostics. The diags tested the IOC board on the back of the chassis and the system RAM. All of the diags passed.
We are working on the Dual-Diskette chassis today. We removed the top and front covers of the chassis, and vacuumed out the accumulated dust and dirt. We disconnected the DC power connectors from both diskette drives, and connected the AC power cord to a Variac. We slowly turned the diskette drive spindles to unstick the belts from the pulleys and to make sure that everything was free.
We set the Variac to 0%, turned the power switch on the front of the diskette chassis on, turned the power switch on the Variac on, connected three DVMs to the diskette DC power connectors so we could measure the +5VDC, -5VDC, and +24VDC outputs. The Variac lets us adjust the AC voltage going into the Dual-Diskette chassis.
We slowly ramped the Variac output until we saw about 1.5VDC on the +5VDC output. We left the Variac at this setting for about 10 minutes to let the capacitors reform a little. We increased the Variac output to about 25% and the DC outputs were 2.04VDC, -1.90VDC, and 6.6VDC. Looking OK so far.
We increased the Variac output until the +5VDC output read 3.0VDC. The other outputs were -3.43VDC, and 9.9VDC. The right diskette drive AC motor spun up, and with a little help the left one did too. We also got the chassis cooling fan to spin slowly. We left the Variac at this setting for 10 minutes. The bearings in the diskette drives are a little noisy. Hopefully they will quiet down after they run for a while.
We increased the Variac output until the +5VDC output read 4.0VDC. The other outputs were -4.47VDC, and 14.3VDC. The left diskette drive made a lot of noise, and then got quieter. We left the Variac at this setting for 10 minutes.
We increased the Variac output to 60%. The DC outputs were 4.98VDC, -4.98VDC, and 24.2VDC. The chassis cooling fan is running faster, the diskette drives are getting quieter. Nothing is smoking, and nothing is too warm.
We increased the Variac output to 100%. The chassis cooling fan is running at full speed. The voltages are the same. We turned the Variac down to 0%, Connected the DC power to one diskette drive, ramped the Variac to 100%, and the DC voltages are the same.
We connected the dual-diskette chassis to the MDS-800 that we know works OK, inserted a CP/M 2.2 diskette into drive 0, and were able to get it to boot! So we now know that the right diskette drive works OK. We tried to list the directory of the left diskette, and ISIS said that the drive was not ready. Something to check on Saturday.
We tried to boot CP/M on the MDS-II. It selected the drive, but did not boot. We can swap the diskette controller from the MDS-800 into the MDS-II to see if that is the problem.
We tried the iPSC-202 Diskette Interface and Channel boards, one at a time, in the MDS-800 system. The MDS-800 will boot CP/M from drive-0 in the MDS-II diskette chassis. It will not boot with the Interface board or the Channel board from the MDS-II installed.
It looks like the diskette controller boards and switch settings are different between the two systems. The MDS-800 has a 1001036-04 Revision R Interface board, and the MDS-II has a 101036-02 Revision E. The Priority selector switch was set to 3 on both boards. The MDS-800 has a 1000467-04 Revision L Channel board, and the MDS-II has a 1000467-02 Revision L. Both boards have the switch set to On, On, On, Off, Off, Off, Off, On to set the I/O address to 0x78.
We cleaned the gold fingers on both boards from the MDS-II, fiddled with the switches, and reseated the ICs. If the Channel board from the MDS-II is installed in the MDS-800 it will not boot, and sometimes will not run the monitor. The Interface board from the MDS-II seems to work OK in the MDS-800. After reseating the ICs several times, and reseating the boards in the chassis several times, when both boards from the MDS-II were installed in the MDS-800 it booted both CP/M and ISIS.
The case was broken at the lower left and the top right of the CRT. A little JB weld fixed that.
We put the two, now tested and working, diskette controller boards back in the MDS-II, connected the diskette chassis, put a CP/M V2.2 diskette in drive 0, pressed the RESET button, and were rewarded with a CP/M prompt. We also booted ISIS V3.4 and ISIS 4.1.
Zhao cleaned the keyboard, so that looks and behaves much better now.
The left diskette drive, #1, does not go ready. This is likely a mis-adjustment of the index pulse circuit. That will hopefully be an easy fix.
We replaced IC A54, a 7432, that we temporarily installed when we fixed the IPB board with the correct 74S32 IC. The "S" in the part number means that the IC is made with Schottky technology and is faster than an normal TTL IC.
We looked at the index pulse width from the right diskette drive. It was about 1.1 us, and should be 1.2-2.4 ms. We split the difference an set it to 1.7 ms. The system will not boot from the diskette now. We set the index pulse back to where it was and it will still not boot. We tried the other diskette chassis and it would not boot.
So, it looks like the diskette controller is misbehaving again. We reseated the controller boards and cables, but there was no improvement. We will work on this issue on Saturday.
We decided to fix the diskette chassis from the MDS-II using the MDS-800 because the diskette controller in the MDS-800 works reliably. The first project is to adjust the index pulse for the right drive to 1.7 ms duration. The second project is to determine why the left dri