PDP-8/L Restoration

2/26/11

We pulled the G785 module out of the backplane. This disconnects the power supply from the backplane. We connected a Variac between the AC power source and the 8/L and slowly, over the course of hours, increased the AC voltage to the 8/L power supply. The voltages looked OK, so we put the G785 back in the backplane and powered it on at full AC voltage. After a few minutes smoke poured from the rear transformer in the power supply. Another 8/L owner reported the same smoke and found a shorted power diode in his power supply.

We have another 8/L system that is in poor condition because rodents were living in it. The power supply looks OK, so we can try the power supply in the complete system next week.

7/30/11

Warren and Mike finally had a chance to work on this machine again. We pulled the smoked power supply from the incomplete PDP-8/L and installed in this system. Replacing the power supply is quite a project and involves removing the front panel and a lot of boards.

We noticed that the power supply from the donor system only had one transformer and the failed power supply had two transformers and a toggle swith instead of the keyswitch for poer on. The power supply schematic only shows one transformer, so we are speculating that the failed power supply was substantially modified during its 40 year life.

When we powered on the reassembled system we were rewarded with lights and no smoke. There are some signs of life! After a little experimenting we found that there were some serious problems with the registers. You can see the light pattern after we turned all of the switches off and pushed the Load Address switch. All of the lights should have been off, but many were on. Each of the M220 modules contains 2 bits of the registers. We swapped pairs of the M220 modules around and observed the changes in the light patterns. It looks like only two of the six M220 modules are fully functional. From some quick Googling it looks like the SN7474N chips are a common failure mode for these modules. At least those chips are common and inexpensive.

8/12/11

Ulrich N Fierz of Zurich Switzerland donated two yellow and two orange replacement keys for the front panel.

Mike bought an HP 10526T Logic Pulser, HP 10525T Logic Probe, HP 10528A Logic Clip, and an HP 10529A Logic Comparator. These are the 35 year old tools that are recommended to debug the PDP-8.

Dan found the double-sided Flip-Chip extenders so we can debug the M220 modules in the system.

8/20/11

Mike replaced the missing EXAM switch handle with one donated by Ulrich N Fierz. It works great now. We also found that one of the pivots on the INST FIELD switch is broken so we need to replace that one too with another spare from Mr. Fierz.

Warren and Mike continue debugging the M220 Major Register modules in this system. We started two weeks ago by moving the six M220 modules around in the system and observing the changes in the light patterns. We marked which modules had odd or even or both bit issues. The goal was to get the Memory Address register working because there is no way to Deposit or Examine memory without it.

Some of the Memory Address bits were always on. By observing the lights we could see that some of the Accumulator bits were always on and the corresponding bits in the Memory Address register were always on. The HP 10528A Logic Clip and the HP 10525T Logic Probe were really helpful determining that the AC Enable signal was always on. That was mixing the contents of the Accumulator with the contents of the Switch Register. After chasing the stuck AC Enable signal through the M617 in slot A9 to the M160 module in slot D9 we determined that either the DEC7450 E3 or the DEC7460 chip E4 was defective. There is no way determine which one was defective and we didn't have spare ICs so we swapped the M160 module with one from the parts PDP-8/L. After swapping the M160 the AC Enable signal was working OK. We tested the other two spare M160 modules and those worked OK too. Nice to have some spares! With the AC Enable signal behaving we determined that only one M220 had a problem with the Memory Address register. After a little debugging we found that half of the DEC7474N E4 was defective. We replaced the chip with a "new" TI SN7474N that had a date code only two years newer then the PDP-8/L. The pen in the picture at the left is pointing to the replaced SN7474. After the M220 was repaired we determined that all of the bits in the Memory Address register will load from the Switch register correctly.

After some more experimenting we found that repeated pushes of the newly installed Examine switch do not increment the Memory Address register. If you turn bit 1 of the Switch register on the part of the Memory Buffer is increment. It looks like there is something else wrong with the control logic for the Major Register boards. That will be the project for next week.

We need to get the registers working correctly before we can address any of the other problems with this system.

8/27/11

Old problems:

1. MA does not increment when SR=0, LA, EXAM.

2. MB lower bits seem to increment when SR=1; LA, EXAM,EXAM,EXAM...

2b. Two MB bits (bits 4,5?) seem to toggle together

i.e. not increment like the lower bits (0 to 3?)

Debugging problem 2:

Looking at MB11 (AB02 M220)

(Schematic D-BS-8L-0-9 Major Register Gating, Sheet 3, Zone 1 & 2)

REG BUS 11 is showing incremented value (wrong).

ADD output is also wrong.

Looking at AND-OR terms, SR ENABLE is ON (wrong) when EXAM,EXAM...

Looking at SR ENABLE

(Schematic D-BS-8L-0-4 Reg. Output Gate Control, Zone B4)

A08 M617 pin E1 is SR ENABLE.

A08 M617 pins A1,B1 (inputs) are wrong.

Driven by C12 M115 pin U1.

C12 M115 inputs P1,R1,S1 are okay.

So, C12 M115 E2 7410 is bad. Swapped in a spare. Works (does not increment).

Note: At some point, we determined SR=2 causes MB10 and up to increment.

Now, it makes sense. Since SR ENABLE was incorrectly being enabled, it was ADDing the SR to MEM read value, which was being written back to CORE (remember: CORE read is destructive, so it writes back the MB value).

So, CORE seems to read and write but always at 0000 (Problem 1: MA does not increment)

Problem 2B has changed. The affected bits seem to be stuck on.

We tried swapping:

Major register bits (AB02 thru AB07 M220s),

Sense Amps (A18,A19,A20,B18,B19,B20 G020s).

Inhibit Drivers (A23,B23,B24 G228s)

Much head scratching...(what's really in memory????)

Eventually, we decided all M220s seem okay, but 6 bits are stuck either high or low.

Current problems:

1. MA does not increment when SR=0, LA, EXAM, EXAM...

2. 6 memory bits are stuck high or low.

New problems noticed:

3. RUN -> RUN light. STOP does not stop, but SINGLE STEP does stop.

4. ION is on (related to problem 1?).

9/10/11

If you do a Load Address and then RUN, the STOP key doesn't work. Pushing SINGLE STEP will stop the processor.

Starting in section C2 on page D-BS-8L-0-2 of the DEC-8L-HR2A-D schematics, the run flip-flop is on the M216 module in slot C06 so we started looking there.

We first looked at the POWER CLEAR-N signal on pin R1. We saw a 230 ms pulse with a 30-40 ms up slope. That is OK.

Next we looked on pin N1 for the TP3 pulses. They were there with a 1.66 usec period, about 600 KHz. That is OK.

Next we looked at the M160 module in slot D09. The E1 pin went high when the STOP key was pressed. high for stop (OK). That is OK.

We looked at the F SET signal on pin F1 and found that it was always low.

We then moved to the M111 module in slot C07. It is in section D5 on page D-BS-8L-0-3 of the schematics. We found that the F SET-N signal on pin M2 was always high.

We moved to the M117 module in slot C11. It is in section C5 on page D-BS-8L-0-3 of the schematics.

The D SET-N signal on pin D1 was always high. That is OK.

The E SET-N signal on pin C1 was always high. That seems OK.

The BREAK OK-N signal in pin B1 was always high. That is OK.

The SPECIAL CYCLE-N signal on pin A1 was always low. That is wrong.

SPECIAL CYCLE is WORD COUNT or CURRENT ADDRESS. Sounds like it is part of the Data-Break facility that is not installed.

We looked at the M113 module in slot D12. It is in section B2 on page D-BS-8L-0-3 of the schematics.

The SPECIAL CYCLE signal on pin N1 was always high which is wrong. We actually found that the signal was at 1.7 V, neither high or low.

That means that the DEC7400N E2 is bad. We tagged the module for future repair.

We replaced the defective M113 with a NOS one from a recent donation. Now the SPECIAL CYCLE signal on pin N1 is always a solid low.

We traced the SPECIAL CYCLE signal back through pin D2 on the M111 module in slot D13 at section B2 on page D-BS-8L-0-3 of the schematics

The SPECIAL CYCLE-N signal on pin D2 was always high. Much better!

We looked at the M117 module in slot C11 at section C5 on page D-BS-8L-0-3 of the schematics.

The SPECIAL CYCLE-N on pin A1 was always high. Looks good!

The E SET-N signal on pin C1 looked strange.

We moved to the M115 module in slot C09 at section D4 on page D-BS-8L-0-3 of the schematics.

The E SET START signal on pin V1 pulses high once per power-up.

The INT OK-n signal on T2 is high.

The signals on U2, and V2 are high.

The current behavior is:

LINK is not cleared by START.

If you set the switches to 0000, then LOAD ADDRESS, set SINGLE STEP on, and push START; FETCH is on. That looks OK.

We probably got confused by the E SET signal behavior because the 5000 JMP and 7000 NOP instructions do not have an Execute cycle.

We set the switches to 0000, then LOAD ADDRESS, then DEPOSIT, and continued with the E SET signal.

We looked at the M117 module in slot C11 at section C5 on page D-BS-8L-0-3 of the schematics.

The F SET-N signal on pin E1 is HIGH because the BREAK OK-N signal on pin B1 is LOW. This is not correct.

We continued with the M117 module in slot C11 at section C2 on page D-BS-8L-0-3 of the schematics.

The BREAK OK-N signal on pin J2 is LOW. This is not correct.

The BRK SYNC signal on E2 is always HIGH. This is wrong.

We moved to the M216 module in slot B11 at section B2 on page D-BS-8L-0-3 of the schematics.

The BRK SYNC signal on pin V1 was always high (never pulsed low).

The MANUAL PRESET-N signal on pin U2 (clear?) pulsed low at start.

The BRK RQST-N signal on pin T2 was always high (ok).

Pin V1 is actually Q-N output and pin U2 is PRSET-N.

This means that the DEC7474N E2 is bad.We tagged the module for future repair.

We replaced the M216 module at B11 with a NOS (not sealed bag) module.

Now STOP works and the FETCH and EXECUTE lights cycle. This is some real progress.

At this point it looks like we fixed a major problem with the BRK SYNC-N signal so that the FETCH and EXECUTE cycles work, but we broke some other behavior with LOAD ADDRESS. Sometimes when we press the LA key the SW register contents are not loaded into the MA register. We will need to back out these module swaps to see if we can determine what we fixed and what we broke. I will fix the broken modules so we can put them back in the machine to see if it behaves better. We assumed, but really don't know if the NOS modules was OK.

10/08/11

During the last debug session we replaced the broken M113 in slot D12. This fixed the floating SPECIAL CYCLE signal and allowed the FETCH/EXECUTE cycles to work, but broke the Load Address switch.

We replaced the NOS M216 in slot D12 with another one, but is made no difference in the behavior.

We put the NOS M113 back in slot D12 and now LA switch works. Well, at least it worked once. Subsequent operation of the LA switch did not work correctly.

We set the switches to 0000, operated the LA, DEP, DEP 0000 LA SS

START fetches, CONT executes CONT no lights

Our guess is that fixing the SPECIAL CYCLE signal unmasked yet another problem in the 8/L.

We put the broken M113 slot D12 so we could debug LINK not cleared by START.

Looking at LINK not cleared by START.

We tried tried storing CMA CML instructions in core and executing them.

0000 LA 7020 (CMA CML) DEP MB is 7020

0000 LA EXAM doesn't read

trying to DEP at non 00, it appears that

EXAM clears MA and DEP clears MA

We put the NOS M113 back in slot D12 and verified that LA is not working.

Random MA, START does FETCH/EXECUTE.

On the M617 in slot B08 pin M1 is high, pulse low on LA (ok). all switches pulse it except CONT (ok).

Set the switches to 0000, did a LA, MB = 4010.

On the M220 in slot AB02 looking at enable signals.

We saw a pulse on NO SHIFT AE1 (ok), always high PC ENABLE BS2 (bad), pulse on MEM ENABLE BU2 (ok? transfer from mem).

On the M617 in slot A08 pin V2 signal PC ENABLE low after power, stays high after EXAM. With V2 high, T2 is always low.

On the M113 in slot B13 pin E1 signal F SET is always high after first EXAM, no pulse lo. Pin D1 Signal TS4 is always high after first EXAM, no pulse lo.

On the M216 in slot C04 pin V1 low, pulse high on LA, EXAM, DEP.

We operated the START switch (running, FETCH and EXECUTE flickering)

The signals on pins V1 & V2 are in the wrong state. Pin U2 always low (bad). Pin N1 TP3 pulses (ok).

On the M113 in slot C05...

START (running, FETCH and execute flickering)

Signal TP3 on pin A1 pulses (ok), signal IOT-N on pin B1 always high, pin C1 pulses (ok), pin D1 pulses (ok), pin E1 always low (bad?), pin K1 always low, pin J1 always hi, pin H1 soft high !!!

In the M310 in slot D08...

Pin F1 soft high, the 7440 (E1) pin 8 is output F1 soft high, pins 9,10,12,13 are low.

The M310 in slot D08 is defective. We tagged it for repair and replaced it with NOS part.

LA works now! Setting different addresses + LA gives different MB (constant for same address) so it looks like we can read core again.

Current issues.

EXAM doesn't inc MA, LINK is always on (START should clear LINK), and DEP changes MA.

We tried the switch sequence:

0000 LA 6000

0001 LA 0000

0002 LA 0000

0003 LA 0000

0004 LA 0204

0005 LA 0000

0006 LA 0000

0007 LA 0000

0004 LA 0004 DEP MA is 6214 MB is 0004

0000 LA 6000

0004 LA 0204

6214 LA 0000

6213 LA 0000

We cannot tell if DEP changes memory.

At this point we decided to look a the simpler problem of LINK not being cleared on START. It appears that the AC is cleared by START.

We looked at the M216 in slot B11 which contains the LINK Flip-Flop.

Pin L2 signal clock - START pulses, Pin M2 signal data always high.

We looked at the M160 in slot B10 which contains the LINK data logic.

Pin R1 output is always low!!! We found that LINK is not always set at POWER on. Signal POWER on with LINK high

Pin R1 output high, pin D1 RIGHT SHIFT low, pin F1 DOUBLE RIGHT SHIFT low, pin J1 NO SHIFT high (no pulse on LA,START), pin L1 LEFT SHIFT low,

pin N1 DOUBLE LEFT SHFIT LOW, pin V2 ADDER L-n always low (no pulse on LA,START)

We looked at the M160 in slot A10.

Pin V2 is always low (no pulse on LA,START), pin V1 low, (ok), pin S1 high (ok), pin U1 high (no pulse on LA, START)

We looked at the M160 in slot B10

Pin U2 is always high CARRY OUT 0-n.

We looked at the M160 in slot A12, pin V2 signal L ENABLE is always low (bad?), Pin U1 OP1 low (ok), pin V1 KEY ST tracked the START key (ok),

pin U2 MFTS2 pulsed on START.

We replaced M160 in slot A12 with NOS part and now LINK clears at START!!!!!!

We tagged the defective M160 for repair.

11/19/11

Current issues.

EXAM doesn't increment MA

DEP changes MA.

Debugging.

We decided to look at the issue where EXAM and DEP doesn't increment MA, and MA has the wrong value after operating either switch.

To save cycles the PC is written into the MA during T1 and the MA+1 is written into the PC during T2.

The PC is not displayed on the front panel so we needed to insure that LA actually sets the PC correctly.

Bits 4 and 5 of the MA contained a 1 & 0 after EXAM or DEP so we put the M220 from slot AB05 on extender.

IC E9 pin 3 = no strobe when LA was activated so, PC_LOAD is always low.

We put the M617 from slot B8 on an extender and looked at E1 pin 6. It is low.

E1-1,2,4,5 are all floating.

E1-2,4,5 is driven by A13

We put the M160 from slot A13 on an extender. E1 pin 8 is floating.

We replaced the M160 with one from the parts machine.

Now, LA + EXAM + EXAM yields incrementing MA, but MB is always 6034.

so we made some progress with the MA, but the memory is not working.

We swapped The M160 in slot A13 with the M160 in slot D9.

The behavior was the same so we put the M160s back where they were.

We decided to investigate why the MB was always 60xx.

We put the M216 in slot D16 on an extender and started looking at the chain of flip-flops that control the memory cycles.

The MEM START signal is present at on pin B1.

We looked at the CYCLE & READ flip-flops. There were no clock pulses and the outputs were static.

We put M113 in slot C15 on an extender and looked at pins A1: strobed; C1: strobed.

We put the M310 in slot D15 on an extender and looked at pin H2: strobes.

We put the M617 in slot D17 on an extender and looked at pin S1: strobes once per power up, M1 strobes every time EXAM & DEP are activated.

We need to look at the INHIBIT(0) signal.

We put the M216 in slot D16 on an extender and looked at pins R2 & P2. They strobe every time EXAM & DEP are activated.

We put the M617 in slot D17 on an extender and looked at pins R1 & P1. They strobe every time EXAM & DEP are activated. Pin S1 did not change.

(note: card is REV C, schematic is E)

We replaced the M167 with a NOS REV A, part but the behavior was the same. We put the original M167 back.

We pulled the M216 in slot D16 and saw continuous strobes on pin S1.

That means that the output of the READ flip-flop is connected to the MEM BEGIN* signal.

We swapped the M216 in slot D16 with card from parts machine....no strobes on pin S1 of the M617 in slot D17.

We tried 4 different M216 boards from the parts machine. All have different broken behavior.

The bad behavior includes: bad low output (logic probe shows 'floating'), stuck flops, 'one time' flop, etc.

The "best" broken M216 toggles CYCLE, READ, INHIBIT, but not WRITE.

To continue debugging we will need to repair an M216. Fortunately Warren donated a pile of SN7474 chips.

It is amazing how many broken SN7474 chips are in this system

12/03/11

Current issues.

Memory is not read or written on EXAM or DEP operation.

Debugging.

We looked at the M216 module in slot D16 because that Flipchip contains all of the SN7474 flip-flops that control the memory states.

See page D-BS-8L-0-13, sections D2 through D7 in the schematics.

The MEM_START signal on pin B1 pulses if you operate the LA, EXAM, or DEP keys. This is OK.

We looked at the READ flip-flop. The READ(1) signal on Pin L1 always high. The READ(0) signal on pin M1 pulses high.

The READ(1) signal is connected to a lot of other Flip-chips so we pulled the G228 modules in slot C25 & D25, and the M360 module in slot C17 (no strobes, no XY power select).

We looked at the M310 module in slot D15. See page D-BS-8L-0-13, section C4 in the schematics.

The CYC_DONE signal pulses positve if you operate the LA, EXAM, or DEP keys. This is OK.

We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics.

The MEM_BEGIN pulses signal on pin S1 shows a single pulse.

On pins R1 &P1 the INHIBIT(0) signal pulses.

The signal on pins M 1& N1 pulses.

We looked at the M113 module in slot C15. See page D-BS-8L-0-13, section D2 in the schematics.

The signal on pin F2 (sets inhibit FF) pulses low.

The signal on pin K1 (sets write FF) pulses low.

We looked at the M216 modlue in slot D16. See page D-BS-8L-0-13, section D5 in the schematics.

The signal on pin L1 READ(1) shows a single pulse after power up.

The signal on pin K1, MEM_BEGIN/ (sets read FF) shows a single pulse.

We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics.

The signal on pin S1, MEM_BEGIN/, shows a single pulse low and then stays high.

The signal on pins R1 & P1, INHIBIT(0), pulses low.

The signal on pins N1 & M1 pulses high.

We swapped the M617 module in slot D17 with another spare. It made no difference so we restored the original.

We pulled the G020 modules in slots A18, A19, A20, B18, B19, and B20 to isolate the problem.

We looked at the M617 module in slot D17. See page D-BS-8L-0-13, section D4 in the schematics.

The MEM_BEGIN signal on pin S1 shows a single pulse and then stays high.

The signal on pins R1 & P1, INHIBIT(0), pulses low.

The signal on pins N1 & M1 pulses high.

We swapped the M310 modules in slots D14 & D15. See page D-BS-8L-0-13, section C4 & C5 in the schematics.

The signal MEM_BEGIN/ signal on pin S1 of the M617 module in slot D17 was stuck high.

This behavior was worse so we restored them to their original positions.

We swapped the M310 modules in slot D14 with one from the parts machine and observed the same single pulse on pin S1.

We swapped the M310 modules in slot D14 with with another one from parts machine and observed the same single pulse on pin S1.

We swapped the M310 modules in slot D15 with with another one from parts machine and observed multiple pulses on pin S1. Much better!

We reinstalled the G020s, G228, and M360 modules. The signal MEM_BEGIN/ signal on pin S1 of the M617 module in slot D17 still pulses, but the system will still not read/write memory.

We decided to do a Sanity Test to make sure that the M310 module in slot D15 was causing this problem.

The signal on pin S1, MEM_BEGIN/, in the M617 shows multiple pulses.

We restore original M310 module into slot D15 and observed just a single pulse on pin S1.

We reinstalled the M310 module from parts machine into slot D15 and observed multiple pulses on pin S1.

So the M310 really is bad, so we tagged it for repair.

We got tired of replacing the memory control flip-flops on the M216 board in slot D16 one at a time and just replace all three . That helped, but didn't fix the memory problems.

12/09/11

Current issues.

Memory is not read or written on EXAM or DEP operation.

Debugging.

Since the memory control logic seems to be working correctly now I looked at the eight G221 X and Y memory selectors to see if the MA was getting decoded into core memory selects correctly.

See page D-BS-8L-0-15 and D-BS-8L-0-16 in the schematics.

I started with the G221 module in slot C23 which decodes the MA00(0), MA01(1), and MA02(1) signals.

The SN7440 at E1 was defective so the X select signals were either missing or there were simultaneous selects.

The G221 module in slot D24 had a defective SN7400 at E3.

I replaced all three modules with a good ones from the parts machine. Most of the G221s in the parts machine were also defective, but I found three good boards.

All of the G221 modules are working correctly now. The broken G221 modules were tagged for repair.

12/22/11

Current issues.

Memory is not read or written on EXAM or DEP operation.

Debugging.

Looked at pin D1 of the G020 in slot B20 to see if the STROBE FIELD 0 signal was present when the EXAM or DEP key was pressed. It was not.

See page D-BS-8L-0-14, section B2 in the schematics.

Looked at pin S2 of the M360 in slot C17 to see if the STROBE FIELD 0 signal was generated. It was not.

See page D-BS-8L-0-13, section C2 in the schematics.

The signals on pins P2 and R2 looked OK. The signal went into the delay line, but did not come out.

I replaced the M360 with one from the parts system. The STROBE FIELD 0 signal was present on pin S2 and the STROBE/ signal was present on pin T2.

Now I see the SW contents in the MB when the DEP key is pressed. Progress, but the memory still does not work.

I could see different data on pins C1 and S1 of the G020 in slot B20 when EXAM was pressed so the sense amps must be working now.

See page D-BS-8L-0-14, section B2 in the schematics.

The memory contents was not getting to the memory bus.

I looked at the M220 module in slots AB02. I could see different data on pins BR1 and BV2 when EXAM was pressed.

See page D-BS-8L-0-9, section B1 & B3 in the schematics.

I didn't see a strobe on MEM ENABLE 5-11 signal on pin BV1, so the data would never be gated onto the register bus.

I looked at the M617 module in slot A08. See page D-BS-8L-0-4, section D7 in the schematics.

The input signal on pins L2 & M2 was floating.

I looked at the M160 module in slot A10.

The output signal on pin R1 was floating.

I replaced the M160 with one from the parts machine. The MEM ENABLE 0-4 and MEM ENABLE 5-11 are working now.

The memory looks like it is partially working now.

I can write and read all zeros to core and it is OK.

If I write all ones and read it back, addresses that end in 5 & 7 contain all ones.

The G221 modules in slots D23 and D24 decode address bits 9-11 so I started there.

I looked at the G221 module in slot D23.

See page D-BS-8L-0-14, section A4-A6 in the schematics.

Chip E3 pin 8 is for addresses ending in 0.

Chip E3 pin 6 is for addresses ending in 1.

Chip E1 pin 8 is for addresses ending in 2.

Chip E1 pin 6 is for addresses ending in 3.

This looks OK.

I looked at the G221 module in slot D24.

See page D-BS-8L-0-14, section A2-A4 in the schematics.

Chip E3 pin 8 is for addresses ending in 4.

Chip E3 pin 6 is for addresses ending in 5.

Chip E1 pin 8 is for addresses ending in 6.

Chip E1 pin 6 is for addresses ending in 7.

E3 pin 8 actually decodes addresses ending in 4 & 5, and Chip E1 pin 6 actually decodes addresses ending in 6 & 7.

The 7400 E2 on the module has a floating output pin.

We don't have any spare working G221 modules so I will replace the 7400 on three broken ones.

12/24/11

Current issues.

Memory is not read or written on EXAM or DEP operation.

Debugging.

I replaced the SN7400 on three broken G221 modules with SN5400 Mil. Spec. chips that Warren donated, so we hopefully have three working ones.

I reinstalled the repaired G221 module in slot D24. See page D-BS-8L-0-14, section A2-A4 in the schematics.

I can now read and write core!

I toggled a small instruction test program into core at 200 and it did not run.

I examined core and found that the program that I entered was not there.

I toggled the same instruction test program into core at 0 and it runs, but the contents of the AC are not displayed on the front panel.

When the system is powered on there is random data in the AC.

The first instruction in the test program clears the AC. This works OK, but none of the other AC related instructions work.

I checked all core locations with just one address bit on and found that core locations with the 3, 4, or 5 bit on cannot be written.

The G221 modules in slots D18 & D19 decode the 3, 4, and 5 address bits.

The G221 module in slot D19 correctly decodes the 4, 5, 6, and 7 bit combinations.

See page D-BS-8L-0-15, section A2-A4 in the schematics.

In the G221 module in slot D18, the SN7440 chip E2 does not drive pins 6 & 8 low.

See page D-BS-8L-0-14, section A4-A6 in the schematics.

I replaced it with one of the repaired modules, but core locations with the 3, 4, or 5 bit on still cannot be written.

I swapped the G221 modules in slots D18 & D19 for the modules in C18 & C19 to see if the addressing problem would move.

There was no change in the behavior, so I put them back in the original locations.

At this point I think that everything that decodes memory addresses is working correctly and really didn't know what to try next.

The only other thing that I could think to try was the G228 modules in slots C25 & D25.

See page D-BS-8L-0-13, section B2-B4 in the schematics.

I swapped the two modules and the memory behavior was very different.

I replaced the G228 module in slot C25 with a NOS module from our spares and now all of core works!

I toggled a small instruction test program into core at 200 and this time it ran.

It still failed as soon as the program tested the contents of the AC after an instruction.

12/27/11

Current issues.

The AC is not affected by any instructions.

Debugging.

Dan and Mike worked on the AC problem today.

I suspected that the AC LOAD signal was not loading the AC from the REG BUS. See page D-BS-8L-0-8, section D8 in the schematics.

I put the M220 from slot AB04 on the extender and was surprised to see the AC LOAD signal activated when the CLA instruction was executed.

The two AC bits in this particular M220 were usually set to on at power up. The 0 and 1 output bits of the SN7474 corresponded to the lights on the front panel.

Executing the CLA instruction cleared the the AC and changed the 0 and 1 output bits of the SN7474.

Other AC related instructions also activated the AC LOAD signal, but did not change the contents of the AC.

At this point we decided to see if the bits in the instructions were getting decoded correctly.

We looked at the outputs of the instruction decoding logic on page D-BS-8L-0-3, section B6 & C6 in the schematics.

We put the M111 from slot C07 on the extender.

The JMS & JMS/, JMP & JMP/, IOT & IOT/, OP 2 & OP 2/ signals were all active when one of those instructions was executed.

The OP 1/ was active, but the OP 1 signal was always low.

We replaced the M111 with two different spares and decided that something connected to the output must be pulling the signal low.

We looked through the signal list that Vincent Slyngstad gave us with the intention of pulling boards that connected to the OP 1 signal.

I intended to pull the M160 board in slot A12, but accidentally pulled the one in slot A13.

The OP 1 signal worked OK with the M160 removed.

We found several defective M160 boards in this system and in the parts system so it was not surprising.

We did not have a spare M160 so we swapped the ones in A12 and A13.

The OP 1 signal was tied low.

Removing the M160 in A13 restored operation of the OP 1 signal.

Since the OP 1 signal does not connect to the M150 in A13 we decided to try pulling other modules that connected to the OP 1 signal.

We tried the M113 in B13, the M160 in A12, and the M115 in A11.

Removing the M115 in A11 restored operation of the OP 1 signal.

We replaced the M115 with one from the parts system.

The OP 1 signal was working again and we saw changes in the contents of the AC.

We tried a number of little test programs from David Gesswein.

The CLA, CLL, CMA, CML, RAR, RAL, RTR, RTL, IAC, OSR, STL, GLK, CLA IAC, and CLA CMA instructions worked OK.

We also found that the JMP, ION, IOF, KRB, and KRS instructions worked OK.

None of the instructions that conditionally skip based on the contents of the AC work.

I think that the memory address accessed in the Defer cycle is always 0.

12/29/11

Current issues.

Need to test all instructions.

Debugging.

We tried the SZA, SNA, SMA, SPA, CML, SNL, SZL, SKP, OSR, CLA & CLL, and they all work.

That means that the SKIP flip-flop is working OK.

The SKIP flip-flop is located in the M216 in slot B11 and that module is new.

The CLA and CLN instructions clear both the AC and the Link at the same time.

ISZ clears the AC and writes the MA into core pointed to by the MA.

It should move the AC -> MB and then write the MB to core pointed to by the MA.

DCA has 0 in the MB during the E phase so I don't think that it is writing to core.

This probably has the same problem as the ISZ instruction.

12/31/11

Current issues.

Need to test all instructions.

Debugging.

We tried the CLL instruction again. It clears both the AC and the Link. That is not OK.

The CLA instruction clears only the AC so that is working.

The CIA and LAS instructions work OK.

The AND instruction didn't work.

We looked at the instruction decoding signals on the M111 module in slot C07.

Neither the AND signal on pin E1 or the AND/ signal on pin D1 were there.

We looked at the M115 in slot C09.

The output on pin H2 of the 7410 chip was floating when it should have been driven high or low.

We marked the E1 chip on the M115 as bad and set the board aside for repair.

We installed a M115 from the parts system and verified that the AND/, TAD/, ISZ/, and DCA/ signals were working.

The AND instruction works if the addressed cell is 0 and is on the current page, or the zero page.

The AND instruction also works if the indirectly addressed cell is 0, and cell 0 contains any address.

During TS4/TP4 the Sense Register bits 5-11 are not getting put in the MA.

This issue is the same for all instructions that reference memory.

1/2/12

Current issues.

Look at the memory reverence instructions to find out why they don't put the address in the MA.

Debugging.

I tried to write to 7777 with the MEM PROT switch on. The PROT light lit and it did not write to core. Perfect!

I looked at the M220 in slot AB04, D-BS-8L-0-9, section A8 in the schematics.

The MEM ENABLE 5-11 signal toggles during the FETCH cycle, but it does not load the address part of the instruction in the MA.

Without a 'scope connected it is difficult to know if the MEM ENABLE 5-11 signal is part of fetching the instruction, or loading the address part of the instruction.

I decided to see if TS4 and TP4 are working.

I looked at the M216 in slot C4, D-BS-8L-0-3, section D5 in the schematics.

TS4(0) is low and blinks high.

TS4(1) is high and blinks low.

TP4 is low and blinks high.

Everything looks OK.

I looked at the M117 in slot C13, D-BS-8L-0-4, section C5 in the schematics.

TS4(1) on pin F1 is high and blinks low during FETCH or EXECUTE.

Pin H1 is high during the FETCH cycle.

INT OK/ on pin J1 is always high.

PE ENABLE/ on pin K1 is high during the EXECUTE cycle.

Pin L1, the output, is floating. This would prevent MEM ENABLE 5-11 during TP4.

I replaced the M117 with one from the parts system, and tagged the broken one for repair.

All of the memory reference instructions are working now.

I tried all of the toggle-in test programs from David Gesswein.

Everything works except the program that copies the SW to the TTY continually loops on the TSF instruction.

I put the M707 in slot CD31 on the extender.

The TTO CLOCK/ signal on pin DP2 looks OK, D-BS-8L-0-12, section B7 in the schematics.

The 0 output of the FREQUENCY DIVIDE flip-flop was floating.

I replaced the M707 in slot CD31 with a NOS module and tagged the broken one for repair.

The test program still looped on the TSF instruction.

The TELEPRINTER flip-flop was set and cleared, but TTO SET/ on pin DJ2 was always low.

The IOP 1 signal on pin DH2 never strobed, D-BS-8L-0-12, section C3 in the schematics.

I put the M115 in slot D04 on the extender.

I/O ON(1) on pin D2 is high.

IOP A(1) on pin E2 pulses high.

MB11(1) on pin F2 is high during the FETCH cycle.

IOP 1/ on pin H2 is always high.

I replaced the M115 in slot D04 with one from the parts system, and tagged the broken one for repair.

Now IOP 1/ on pin H2 pulses low.

The test program gets past the TSF instruction now.

I made a cable to go from the AMP connector on the W076 in slot D33 to the AMP connector on a VT220.

The program that copies the SW to the TTY actually wrote to the screen on the VT220!

I tried a TTY echo program, but the program looped on the KSF instruction.

I replaced the M706 in slot CD32 with a NOS module and tagged the broken one for repair.

Now anything typed on the VT220 is echoed to the screen.

1/14/12

The system has worked OK the last two Saturdays we turned it on. Looks like it might me fixed.

Now we can use it to test the modules in the PDP-8/I.

Warren tried his home-build RS232 to current-loop converter. At low speeds the laptop to 8/L interface is working OK.

At high speeds it fails. When he gets this working we can use it to load diagnostics into the 8/L.

1/28/12

We powered up the 8/L so that we could try Warren's RS-232 to Current-Loop adapter.

Last time we left a TTY echo program in the system, so all we had to do was a LA and a START.

Well, the system froze in the Fetch state.

It would signal step fine, but froze when run at full speed.

The program that we left in the system was:

0000 7001 IAC increment AC

0001 6046 TLS load teleprinter buffer, print/punch, clear flag

0002 6041 TSF skip if teleprinter flag

0003 5002 JMP 0002

0004 5000 JMP 0000

We decided to start at the beginning and see if timing states were working.

We put the M216 module in slot C04 on the extender.

We turned on SINGLE STEP and the CONT switch was activated all 4 states (TS1, TS2, TS3, TS4) pulse. That is good.

When we turned off SINGLE STEP and hit START.

We only one saw one timing pulse after START. That is not good.

We checked the states of the Timing State flip-flops in section D6-8 of the schematic page D-BS-8L-0-2.

Put the M216 in slot C04 in the extender and found that pin B1 only pulsed once. Not good.

So the system was stuck in the TS1 state.

We put the M113 in slot C02 on the extender to see how the signal on B1 of the M216 module in slot C04 behaves.

When in SINGLE STEP, operation of the CONT switch sends a pulse into pin R2, then S2->R1->S1. Looks OK.

When running we should see a pulse on pin P1, then S1. It was not there. Not good.

We put the M115 in slot D04 on the extender.

Pins A1 and C1 were high. That looks good.

Pin B1 is low, so the system was stuck in the PAUSE state.

We were executing IOT instructions in our test program.

The PAUSE state is used with IOTs to stretch the instruction cycle time.

We tried a two instruction program with just an IAC and a JMP.

That ran fine, so we knew the problem was specifically with the logic for the IOT instructions.

We put the M216 in slot C04 on the extender.

When in SINGLE STEP the PAUSE flip-flop worked as expected.

When not in SINGLE STEP, we only saw one pulse on pin H1.

We put the M310 in slot D05 on the extender.

When in SINGLE STEP we saw the expected pulses on pins H2 and F1.

When running we only saw one pulse on H2 and F1.

We put the M113 in slot C05 on the extender.

The I/O END\ signal on pin K1 looked OK.

We put the M310 in slot D07 on the extender.

There was no output on pin F1.

The 0.05us tap that generates the I/O ROT signal looked.

The NAND gates seem to work (module schematic is REV D; bad module is REV (A or B)).

After some probing it appears to be transistor Q1 bad.

We tagged the module as BAD and set it aside for repair.

We installed on of the M310 modules from the parts 8/L and everything seems to work OK now.

We ran the test program and were able to echo characters from Warren's laptop through the 8/L.

So, that means that the 8/L is alive again and Warren's RS-232 to Current-Loop adapter works.

We toggled in the RIM loader, ran it, and sent the BIN loader (DEC-08-LBAA-D) to the 8/L from Warren's laptop.

It was very nice to see blinky-lights on the front panel while the RIM loader ran.

We halted the RIM loader and checked part of the BIN loader instructions. It actually looked OK!

We started the BIN loader running and sent very short binary file "MAINDEC-08-D1AA-PB", the PDP-8 memory power ON/OFF to the 8/L.

We saw more satisfying blinky lights, and it halted with LINK set and AC=0. That indicates a good checksum!

Time to leave. Starting to pack up...

Mike tells Warren to run the diag: "Don't leave me hanging!"

Found test document for rev C "MAINDEC-08-D1AC-D.pdf".

The operating procedure is; LOAD ADDRESS 0014, START, program halts at 0042.

Then LOAD ADDRESS 0001, START, the program should loop.

The program halted at 0055. it's the error halt.

So, it looks like the might still be some memory problems.

We need to look at memory locations 0011, 0012, 0007, and 0010 to determine where the memory error was seen and what the bits were.

We will save this for next weekend.

2/4/12

Today the 8/L was the test bed for the modules in the 8/I.

We started testing the modules one-at-a-time and found a similar selection of defective modules.

2/11/12

We continued using the 8/L as the test bed for the modules in the 8/I.

We proved that most work OK, and found 7 more broken modules.

2/28/12

Last Thursday was the one year anniversary of starting on the 8/L project.

This system seems to be very reliable now.

We continued using the 8/L as the test bed for the modules in the 8/I and found many broken modules.

Using the 8/L for testing the 8/I modules is really saving a lot of time.

We have accomplished in just two months work in the 8/I what it took 10 months to accomplish on the 8/L.

We are also a lot more familiar with the design and function of this system and our test procedures, so that helps too.

5/19/12

We used Warren's 20 mA current-loop to RS-232 converter to load some diagnostic programs into the 8/L.

The Random JMP-Test, Random JMP-JMS Test, and the Random ISZ Test all worked fine.

The Instruction Test - Part 2B failed miserably. Not sure why.

We tested the M707 TTY transmitter module that has taken 5 attempts to fix. It is finally working!

6/2/12

We loaded the first instruction diagnostic maindec-08-d01c-pb.bin. It failed miserably.

The contents of core where the diagnostic failed did not match the program listing.

We loaded the maindec-08-d1b1-pm.bin Memory Address test.

It failed at core location 2000, near where the core contents were incorrect from the previous diagnostic.

We found that memory locations 2000 through 2077 did not work.

We swapped G221 memory selectors, but it did not move the address of the failure.

We swapped G228 inhibit drivers, and the G020 sense amps, but that did not change anything.

We pulled the core stack and measured the diodes for the 2000 to 2077 range.

We found one of the diodes was bad.

We replaced it with a 1N4148 diode that we had, but that did not fix the core.

We tested all 512 diodes and found four more bad ones.

We replaced those with 1N4148 diodes that we had, but that did not fix the core.

After doing some more research we found that the 1N4148 is not a suitable replacement for the D672 diodes on the core.

We need to find some 1N3653 diodes so we can repair the core.

We tried the core stack from the PDP-8/I which originally came from the parts PDP-8/L.|

That core stack did not work 100% because it probably needs voltage and current tuning to work in this 8/L.

6/9/12

With a lot of help from the usual PDP-8 experts we narrowed the selection of possible replacement diodes to the ones listed in the table below.

The data sheets for the diodes were not really helpful and were not consistent in the way that the Vf was specified.

I setup a power supply with the voltage limit set to 6V, and the current limit set to the values listed below.

I measured the voltage across the diodes at the various current levels.

The 1N3653 is a pretty good diode, and the FDH333 came in as a close second.

I replaced the 1N4148 diodes that I had previously replaced with FDH333 diodes.

Unfortunately this did not fix the problem with memory in the 20xx range.

Page 20 of the schematics (DEC-8L-HR2A-D_8Lschem_Feb70.pdf) shows the X-Axis Selection.

Warren Stearns gave me another lesson in how core works and patiently showed me the current path for read and write.

To read the core at 20xx the current comes from the X R/W Source at pin T2, through the diode at pin N2,

through the transistor to pin P2 and into the core stack at pin CH2. All of this is on the M221 module in slot C24.

Replacing that module made no change in the behavior.

The current comes out of the core and pin DD2, into pin J2 of the M221 in slot D18, through the transistor to pin K2,

through a diode and out pin T2 to the power supply.

Replacing this module made no change in the behavior.

To write the core at 20xx the current comes from the X R/W Return at pin T2, through the diode at pin J2,

through the transistor to pin K2 and into the core stack at pin DC2. All of this is on the M221 module in slot D18.

The current comes out of the core and pin CJ2, into pin N2 of the M221 in slot C24, through the transistor to pin P2,

through a diode and out pin T2 to the power supply.

That led us back to the diodes on the core stack.

We decided to look at the core current wave forms to how the 20xx range compared to the rest of the core.

Looking at page 10 of the schematics...

The resistor between pins F2 & U2 on the G624 in slot B25 will see both the read and write current for the 00xx through 77xx addresses.

We connected a 'scope across the resistor R1 on the G624, entered a JMP .-1 instruction at 0000 and ran the "program".

We saw two humps on the 'scope, one for read and one for write. Both were the same amplitude.

We tried the same "program" at the other addresses in the X000 address range.

The wave forms all looked the same until we got to the 20xx address range.

In this case the write current was about 20% less than the other address ranges, and the read wave form.

Just for comparison, we replaced the M221s at C24 & D18, but there was no change in the wave forms.

So, now we are back to the diodes on core stack.

There are four diodes on the core stack for the 20xx address range. Two are used for reading, and two are used for write.

Since the wave form for read matched both the read and write for the other addresses we knew that two of the four diodes were OK.

We don't have detailed schematics for the G610 and G611 diode boards on the core stack, so we really don't know where the other two diodes are.

That means that when we look for diodes connected to slot CD22 pin CJ2 and slot CD20 pin DC2 we find eight diodes connected to each pin.

We used the diode function of the DVM to measure the diodes and all looked OK.

Warren suggested that the DVM was using a very low current and that the diode current at 320mA might be very different.

We setup a power supply with the voltage limit set to 6V, and the current limited to 200mA.

We connected the positive side to core stack pin CH2 and the negative side to pin DD2 to check the read diodes for a baseline measurement.

The resulting voltage drop was 2.92V. That was about 0.9V for each diode and 1.12V for the core wiring. This is entirely reasonable.

We reversed the connections and connected the negative side to core stack pin CH2 and the positive side to pin DD2 to check the write diodes.

This time we saw a voltage drop of 6V. This is way too much, and the result of a bad diode.

We went looking at the eight possible bad diodes by measuring the voltage drop across the diodes.

Most measured some very small mV drop, so they were not conducting any current.

I almost burned my finger on one of the diodes when moving the DVM probes. The hot diode was the one that had a high voltage drop.

We found the hot diode and it had a voltage drop of almost 6V.

When I cut out the diode it the glass case broke in half, so that explains why the diode was bad.

I suspect that all of the other diodes that we replaced were probably good enough to work, but would probably have failed in the future.

With the bad diode replaced with an FDH333 the voltage drop was now 2.77V. Looks much better.

Well, now the address range 20xx is working again and I know a lot more about how core memory works.

We loaded the RIM loader and tried to load the maindec-08-d1b1-pm.bin Memory Address test.

It died horribly and left a mess in core.

We checked the read/write capability of the core in the addresses used for the RIM loader and found that we could not set MA7 to a 1.

We immediately suspected the SN7474 for the MA in the M220 in slot AB04.

We put the M220 on an extender and looked at the outputs from the MA flip-flop.

The 1 output would go up to about 0.5V and then go back to 0V. The 0 output would go up just a little and then go back to 0V.

Warren said that a flip-flop will go back to it's original state if it can't drive the output.

We pulled the G221 modules in slots D23 & D24. Now the MA7 bit worked OK.

We replaced the G221 in slot D24 with an untested repaired module and now things looked much better.

We loaded the RIM loader and tried to load the maindec-08-d1b1-pm.bin Memory Address test.

The RIM loader didn't run well and left a mess in core.

We replaced the G221 with another untested repaired module and now everything looked OK.

We loaded the RIM loader and loaded the maindec-08-d1b1-pm.bin Memory Address test.

The documentation on this diagnostic say that the starting address for the Low Storage test is 0000.

The listing shows that 0000 is stored in 0000 and a JMP 1 is the next instruction.

If we start the diag at 0000 it just loops at 0001.

Looking through the listing we can see a reasonable starting address at 0200, so we tried that.

We saw a few errors listed, then the diag ran without any output for several minutes.

During the week we need to find out how this diag is supposed to be run and try it again next week.

If this system passed diags, then we can again use it to test the modules from the PDP-8/I and fix the processor in that system.

6/16/12

We loaded and ran the maindec-08-d1b1-pm.bin Memory Address test.

It is supposed to print "11" about every 28 seconds when it is working correctly.

Well, it didn't. We halted the program and single stepped through it to see what it was doing.

Some of the memory contents were incorrect, so it didn't run correctly.

We reloaded the program and the memory contents looked OK.

When single stepping the program it looked like it was behaving OK.

When we ran the program at full speed some of the memory contents were changed.

We tried a two instruction program; JMP .+1, JMP .-1, to see if the memory contents would not change.

After trying lots of memory locations we determined that anything in the memory addresses xx00, xx10 would changed if the processor ran at full speed.

We immediately though of the G221memory selectors for the Y-Axis.

Changing the four G221s for the Y-Axis one-at-a-time did not change the memory behavior.

We looked at the read & rewrite memory current going through the resistor R1 on the G624 module in slot B25.

When running the two instruction loop both the read & rewrite current pulses looked the same for all of the address.

We though about what modules are connected to the MA, and specifically bit 8.

The M220 in slot AB03 has bit 8 on it in many registers.

We swapped the M220s in slots AB03 and AB04, but that did not change the behavior.

Out of desperation we swapped the G221s for the X-axis, and found that replacing the one in slot D19 fixed the problem.

On close inspection of the failed G221 module we found that the idiot who repaired the module last time (me) replaced the wrong chip.

The defective chip with really light high drive on one of the 7440s was still on the module.

That explained the single step vs. run behavior, but did not explain why this particular module would fix a behavior on address lines that it does not decode.

Rerunning maindec-08-d1b1-pm.bin Memory Address test still didn't give us the expected results, so we decided to test instructions.

We loaded MAINDEC-8I-d01c Instruction Test 1, and single stepped through the tests.

After most of the instructions worked OK, we turned off single step and let it run.

It immediately halted with an instruction failure.

Looking at the test instructions showed that some of the memory locations were not what they should be, and bits were dropped and added.

So now we have a catch-22 situation.

The processor will not run the memory address test correctly, so some instructions may not be working correctly.

The processor will not run the instruction test because some of the bits in memory change when the test is running.

6/23/12

We loaded MAINDEC-8I-d01c Instruction Test 1, and single stepped through the tests.

Everything worked OK until we got to the instructions at 0500. The memory was all zeros.

We swapped the G221 modules at C23 and C24, but there was no change in the behavior.

We swapped the G221 module in D19 and the 0x500 address range works.

We were really happy that it wasn't a wire in the core stack.

We tried just running Instruction Test 1 at full speed, but it halted at 0501.

We looked at the code in the area and found that the contents of location 0500 was all zeros.

We did some more experimenting and found that any instruction at xx00 was replaced with zeros if the program was run at full speed.

We loaded a little program consisting of: IAC, IAC, JMP .-2 would replace the first IAC with zeros.

More experimenting showed that if any of the address bits 6-11 were on, the program would work OK.

We spent the rest of the afternoon swapping all of the G221s, G228s, and G224s.

None of the module changes affected the strange behavior.

We swapped the M617 in slot A9, but that didn't make a difference.

At this point we really don't know what is causing this memory behavior.

6/30/12

We decided to swap all of the modules that have anything to do with memory timing to see if

we could fix the issue where single stepping the processor works, but running the processor erases memory

locations in the xx00 range.

We found out right away that bit 6 was not working for all memory locations.

Replacing the G020 in slot B18 fixed it. We actually put the board back that we took out last week.

We swapped the M216 in D16 & C04, the M113 in C02 & D12, the M115 in D04, the M310 in D06 & D07,

the M111 in C07, the M160 in A10, the G228 in A23, G020 in A18 & A19. None of the swaps changed the memory behavior.

We measured the memory voltage on the G624 module in B25. It was 22.98 with the processor running and 23.29 halted.

We measured the delay on the M360 module in C17. It was set to 148ns.

We decided to measure the delays in the Memory Control logic.

We started with the "MEM START" signal on pin N2 of the M113 in C2.

The delay to pin P2 of the M360 in C17 was 444ns running or halted. Looks reasonable.

The delay to pin S2 "STROBE FIELD 0" of the M360 in C17 was 608ns running or halted. Looks reasonable.

The delay to the "1" data on the test point on pin E1 of the G020 in A17 was 220ns halted and 316ns running.

This looks really strange. This will probably prevent aligning the memory to a delay that will work both running and halted.

The delay to pin F1 of the M310 in D14 was 256ns running or halted. Looks reasonable.

The delay to pin J1 of the M310 in D14 was 332ns running or halted. Looks reasonable.

The delay to pin L1 "RUN" of the M216 in D18 was 312ns running or halted. Looks reasonable.

The delay to read current pulse across the resistor at pins U2-F2 on the G624 in B25 was 376ns running or halted. Looks reasonable.

So, it looks like all of the signal timing is OK both running and halted.

The time from the current pulse to the data in the test point on the sense amplifier changes about 100ns between running and halted.

Maybe this has something to do with the diode replacements that we made on the core stack?

7/5/12

We continued work in the core memory problems. The 8/L maintenance manual includes a Memory Alignment procedure.

We adjusted the memory voltage to 22.5V and looked at the relationship between the STROBE FIELD 0 and the signal

on the test pins E1 & K2 on the sense amps. We found that some bits at some addresses has about a 25ns shift between

running and single-step and others had more than a 100ns shift. We were able to find "good" addresses for all bits,

so the sense amps are all OK. We swapped the G221s and found no difference when looking at the same bits and

address. So that leaves only the core stack as the problem. We swapped the core stack with the one from the 8/I

and there is no bit-shift on any bits at any addresses. This core stack has all original diodes.

7/7/12

We fixed Warren's current to RS232 converter so we could load programs. It seems that the unregulated -30V from the G785

board was more like -40V. This is wired to the W076 module and was a little tough on the 40V rated transistor connected to

the current loop. Warren added a resistor across the 20mA connections to reduce the voltage and it works fine now.

We toggled in the RIM loader, and loaded the BIN loader. Unfortunately BIN loader would not run. We fixed a few corrupt instructions

and tried to load a diag. The AC was not zeros at the end, so we knew that there were more problems.

We loaded the D1B1 Memory Address Test (low) (RIM format). It displayed all kinds of errors in the x6xx and x7xx range. We replaced

the G221 in slot D19 with a repaired but not tested one, but it had worse problems. We tried another, and then another and finally got one

that worked OK. Now the diag runs fine and displays an "11" every 29 seconds. We also tried the D1B2 Memory Address Test (high) and

that also worked OK.

Now the BIN loader loaded and worked fine. We loaded the 8I-D01C Instruction Test 1 which of course failed instantly. The failure pointed

to the the M220 in AB05. We swapped it with a repaired but not tested module and it failed in a different way. We swapped it with another

repaired but not tested module, and another and finally borrowed one from the 8I. Now it will run the instruction diag without problems.

So, at this point the system is looking pretty solid. Next week we will run more diags to prove that it is really running OK.

This week I will replaced the FDH333 diodes on the misbehaving core stack with 1N4149 diodes and see if the single-step/running delay in

the core stack is gone. If so, we can put the borrowed core stack back in the 8I and go back to debugging that system.

7/14/12

We ran maindec-08-D02B PDP-8 Instruction Test Part 2B. Both the TAD and rotate sections run without errors.

We ran maindec-8I-D02B PDP-8I Instruction Test Part 2B. The SZA test at 0232 failed.

We ran maindec-08-D04B PDP-8 Random JMP Test. It periodically prints "04" and runs without errors.

We ran maindec-08-D05B PDP-8 Random JMP-JMS Test. It periodically prints "05" and runs without errors.

We ran maindec-08-D07B PDP-8 Random ISZ Test. It periodically prints "07" and ran for a few minutes without errors. We set SW9=1.

After running for a while we got an spurious interrupt and the diag halted.

We connected 'scope probes to pin P2 and M2 of the M516 module in slot A33 so we could see if there was a TTY interrupt when there should not be.

It ran for more than an hour in this configuration without a problem. We also tried the diag with SW9=0 and it still runs OK.

We ran maindec-08-D1L1 Basic Memory Checkerboard (Low). We ran it for about 10 minutes and didn't see an error.

Running the memory checkerboard without errors is a really good test of the system and the core.

We ran maindec-8I-D01C Instruction Test 1. It rings the bell about twice/second and runs OK.

We ran Warren's pt_info program against the two images if the maindec-8I-D02B that I had. Both showed errors in the paper tape image.

We loaded in an image that Warren made. It halted at 2433 because location 2430 contained the wrong instruction.

We fixed location 2432 and it halted at 3336. This time we fixed an instruction at 3333.

Now it halted at 3321. Fixing the instruction at 3303 fixed it, and we let it run for several minutes.

Now that we thought that the processor was working well, we put the original core memory stack back in.

We ran the maindec-08-D1B1 Memory Address Test for several minutes without an error. It periodically prints "11".

So, now we know that the 1N4149 diodes are OK for a core memory repair.

We ran maindec-08-D1L1 Basic Memory Checkerboard (Low) for about 30 minutes and didn't see an error.

Next week we should run the memory alignment procedure to adjust the memory voltage and the timing.

We put the borrowed core stack back in the 8I so we can get back to debugging that system.

7/20/12

We ran maindec-08-D1L1 Basic Memory Checkerboard (Low) for about 10 minutes and didn't see an error.

I guess that means that the processor and memory are still working.

We ran maindec-8I-D01C PDP-8 Instruction Test Part 1. Everything worked OK.

We installed a repaired M220 Major Registers module in slot AB07, this is for bits 0 & 1.

It would not run at all. On inspection of the M220 We found that I installed SN7453 E12 backwards when it was replaced.

I will fix that this week.

We installed another repaired M220 Major Registers module in slot AB07.

We ran maindec-8I-D01C PDP-8 Instruction Test Part 1. It halted at 1466 indicating a problem with the RTR instructions.

This needs more debugging.

7/21/12

We ran MAINDEC-08-D1B1 Memory address test (low) to make sure that everything was still working OK. It was.

We swapped the G221 in slot C24 with several repaired modules. Some of them worked OK and will be spared.

Others need more debugging and repair. This time we found defective transistors.

We tried all of the G221 modules from the PDP-8/I and found that one was broken. It was replaced with a spare.

I will repair the broken one this week.

We tested almost all of the spare and repaired module; first in Warren's tester and the in the 8/L.

We are starting to build a good collection of tested and working spares.

7/28/12

We ran MAINDEC-08-D1B1 Memory address test (low) to make sure that everything was still working OK. It was.

We tested the two repaired M220 modules by running Instruction Test 1 & 2.

Both worked OK.

8/4/12

MAINDEC-08-D1B1 Memory address test (low) was left in the core from last week, so we ran it just to make sure that

the processor was still working OK. It was!

We loaded and ran MAINDEC-08-D1L1 Basic Memory Checkerboard (Low).

We performed the "memory alignment procedure" while the checkerboard was running and made some adjustments to the memory timing.

We looked at the relationship of the "Strobe Field 0" signal and the ones from the sense amplifiers and increased the delay in the M360 module

so the relationship looked like Figure 5-6 in the Maintenance manual.

We ran the MAINDEC-08-D1L2 Basic Memory Checkerboard (High) for about six hours and checked the timing on all bits. They all look OK.

We even loaded the Focal language interpreter. That worked OK too.

8/13/12

I loaded MAINDEC-08-D1B1 Memory address test (low) to make sure that the processor was still working OK. It was!

I loaded MAINDEC-08-D1L1 Basic Memory Checkerboard (Low) which also ran OK.

I used the system to test repaired M220, G020, and G221 modules. They all worked OK and were put in the spares cabinet.

8/18/12

We loaded MAINDEC-08-D1B1 Memory address test (low) to make sure that the processor was still working OK.

We tested all of the G221 modules from the PDP-8/I and found two that misbehaved.

9/1/12

We loaded MAINDEC-8I-D02B PDP-8I Instruction Test Part 2B and tested the M707 from the 8/I and the repaired M707.

Both worked perfectly for 10 minute diag runs.

We replaced the M216 in slot B11 with the M216 from slot E33 in the 8/I.

The Instruction Test Part 2B diag ran for 25 minutes without a problem, so this is not the misbehaving module in the 8/I.

9/8/12

We loaded MAINDEC-08-D07B PDP-8 Random ISZ Test, and ran for 60 minutes without an error.

We installed the M220 modules from the 8/I and they worked perfectly for a 20 minute diag run.

So, we have eliminated the M220 modules from the ISZ diag problem in the 8/I.

11/18/12

The the PDP-8/L came home for the holidays so I could debug the FPGA based paper tape reader emulator.

Just to make sure that everything was working OK I ran:

• MAINDEC-8I-D02B PDP-8I Instruction Test Part 2B. Works OK.

  • MAINDEC-08-D1B1 Memory address test (low). Works OK.

  • MAINDEC-08-D1L1 Basic Memory Checkerboard (Low). Works OK.

3/19/22

We powered on the system for the first time in 10 years. It is really broken and doesn't respond to pressing most of the front panel keys. Pressing Load Address results in something loaded into the Memory Address, but not what the front panel switches were set to.

3/20/22

Today we started by testing the M220 modules. Four were OK, and two failed on the board tester. We repaired the two M220 modules, but there was no change in the behavior.

4/2/22

We looked at the PC LOAD and MA LOAD signals on the M220 Modules. Neither signal goes active when the START or LOAD ADDRESS switches are pressed.

The All of the KEY signals are present at the input of the NOR gate on the G921 in slot D01, and on the output of the NOR gate. The signals are really noisy from switch bounce.

M700 Manual Timing Generator in slot CD03:

The MFTS0\ signal on pin CN2 of the M700 module in slot CD03 is clean and goes low when LOAD ADDR, START, CONT, EXAM, and DEP are pressed. The MFTS0 signal on pin CM2 goes high when the same switches are pressed. The MFTP0 signal on pin CT2 has a 1 uS high-going pulse when the same switches are pressed. The MFTP1 signal on pin CE2 has a 120 nS high-going pulse when the same switches are pressed. The MFTP2 signal on pin DD2 has a 120 nS high-going pulse when the same switches are pressed. The 0 and 1 outputs of the MFTS1 flipflop are OK. The 0 and 1 outputs of the MFTS2 flipflop are OK.

Load Address

SR ENABLE on pin E1 on the M617 module in slot A08 has a 2 uS high-going pulse when LOAD ADDR is pressed or DEP is pressed. PC LOAD has a 100 nS high-going pulse on pin J2 of the M617 in slot B08. PC LOAD is also present on pin AN2 of the M220 in slot AB07. MA LOAD is not present on pin AK1 of the M220. MA LOAD is not present on pin S1 of the M617 in slot B08. Schematic page 6, TP4\ has a low-going 150 nS pulse on pin P1 of the M617 in slot B08. The M216 in slot B08 failed on the board tester, and showed that chip E3 failed. We replaced the M216 in slot B08 with a tested spare, and now LOAD ADDR works!

Deposit & Examine

Deposit and Examine increment the PC, but do not change the contents of the Memory Buffer. PC ENABLE on pin V2 of the M617 in slot A08 of schematic page 4 has a 2 uS high-going pulse when DEP is pressed.

Things to look at during the next debug session.

Fix the Load Address function, then look at the Examine and Deposit functions.

Diagnostic Passed:

MAINDEC-08-D1B1 Memory address test (low)

MAINDEC-08-D1B2 Memory address test (high)

MAINDEC-8I-D01C Instruction Test Part 1

MAINDEC-08-D02B PDP-8 Instruction Test Part 2B

MAINDEC-8I-D02B PDP-8I Instruction Test Part 2B

MAINDEC-08-D04B PDP-8 Random JMP Test

MAINDEC-08-D05B PDP-8 Random JMP-JMS Test

MAINDEC-08-D07B PDP-8 Random ISZ Test

MAINDEC-08-D1L1 Basic Memory Checkerboard (Low)

MAINDEC-08-D1L2 Basic Memory Checkerboard (High)

The boards replaced so far are:

G221 in slot C23.

G221 in slot D24.

M113 in slot D12.

M115 in slot A11.

M115 in slot C09.

M115 in slot C12.

M115 in slot D04.

M117 in slot C13.

M160 in slot A10.

M160 in slot A12.

M160 in slot D9.

M216 in slot B08 with a tested spare. (4/2/22)

M216 in slot B11.

M216 in slot D16 repaired.

M220 in slot AB?? repaired.

M220 in slot AB?? repaired. Replaced SN7474 E9. (3/20/22)

M220 in slot AB?? repaired. Replaced SN7453 E2, SN7460 E5. (3/20/22)

M220 in slot AB05 replaced with a module borrowed from the PDP-8/I.

G020 in slot B18.

G221 in slot D18.

G221 in slot D19 repaired. Replaced again with a repaired module. Replaced again with a repaired module.

G221 in slot D24 repaired.

G228 in slot C25.

M310 in slot D07.

M310 in slot D08.

M310 in slot D15.

M360 in slot C17.

M706 in slot CD32.

M707 in slot CD31.