MITS ALTAIR #2 Restoration Page

7/25/20

We cleaned the exterior and interior of the chassis. Other than being a little dirty and dusty the system is in very good condition.

Since system may not have been powered on for years or even decades, the first project is to reform the capacitors in the power supply. If you don't reform the capacitors before powering on the system you will very likely destroy the capacitors. We connected a laboratory power supply to each of the filter capacitors in the power supply and slowly brought the lab supply voltage up to the system's operating voltage while monitoring the current. There is an additional +8VDC filter cap installed that is a monstrous 25,000 uF @ 30VDC, in addition to the 4x 3,300 uF 16VDC caps on the filter board.

The filter caps for the +10V supply draws about 12mA when we increase the lab supply voltage by 1V, and the current drops to 4mA after a few minutes. Once the current drops to a minimum we can increase the lab supply voltage again. It finally settled at 14mA of leakage at 8.0VDC. Some of the leakage is through the D1 rectifier bridge, some through the 4x 3,300 uF caps, some through the 25,000 uF cap, and some through the front panel. Good enough to move onto the other voltages.

The second +8VDC supply has just 2x 3,300 uF @ 15VDC caps. It leaks 25mA at 2.0VDC at the start. As we increased the voltage the lab supply went into current limit mode at 100mA and would not go above 5VDC. We increased the current limit and the data LEDs on the front panel lit when the lab supply voltage got above 5VDC. With the lab supply at 8.0VDC the current is 500mA.

The +16VDC settled at 1mA leakage, and the -16VDC also settled at 1mA leakage.

Time to power it on and see if the transformers and diodes are OK. We connected the system to a Variac and slowly increased the AC voltage. Nothing smoked, and the fans started running when we got to about 65VAC. We continued increasing the AC voltage and stopped at 120VAC. Still no smoke.

The backplane voltages should be about +8VDC, and +/-16VDC. On this system the +8VDC was actually 13.9VDC, the +18VDC was +19.1VDC, and the -16VDC was -18.4VDC. The +8VDC is quite high, but will be regulated down to 5V on the boards. The larger than normal voltage drop through the on-board regulator will make the regulators run very hot. We put a 25Ohm resistor across the +8VDC output and the actual voltage dropped to 13.09VDC with a 0.5A load. The +8 supply can make 8A, so we need a bigger load. Connecting 3x 25Ohm resistors results in 12.36VDC.

With the CPU, RAM, SIO, and Diskette controller installed the +8VDC is +11.8VDC. Still quite high. It measured 8.24VDC in Altair #1. The other voltages were +16.6VDC and -17VDC.

When we were fiddling with the front panel we noticed that toggle switch for bit 12 doesn't toggle. We will try to fix it with some contact cleaner, and maybe replace it with one of the spares that came with the first Altair.

The CPU and static RAM board work OK in Altair #1. In Altair #2 the address LEDs are counting and the CPU won't stop. Looks like we need to fix the front panel and replace switch #12.

The boot ROM in the floppy controller starts at 0xF400. I connected the drive to the controller with a short cable, changed the drive select from #1 to #0, and started the CPU. The drive select LED went on, so the CPU is running and some of the floppy controller is working.

8/8/20

We looked at the +8VDC unregulated power supply today and see if we could determine why the output voltage is so high. There are actually two +8VDC power supplies; one from Transformer #1 that supplies 8A to the backplane, and a second from one winding of T2 that supplies 1.2A for the front panel. The schematic says that T1 should supply 7.5VAC RMS, and T2 should supply 8VAC RMS. T1 is actually supplying 10.7VAC, and T2 is actually supplying 14.1VAC RMS. There is only one set of input taps on the transformers, so the only thing that we can do is use a Variac to lower the input AC voltage, or run it as it is and let the onboard voltage regulators run hot.

When the system is powered on the processor is in a random state. The normal procedure is to hold the Stop/Run switch in the Stop position and momentarily press the Reset switch. The Stop/Run switch has no effect on the LEDs. Holding Stop and pressing Reset results in the MEMR, MI, and WO LEDs on, the data LEDs on, and the Address LEDs counting. Pressing RUN turns the STACK LED on, and then pressing STOP turns the STACK LED off. None of the other switches on the front panel have any effect.

You can see the front panel bad behavior here.

The RESET* signal on the backplane goes low when the RESET switch is pressed, so that is OK.

The RUN signal on pin 71 of the backplane is low (inactive) at power on, and stays low after Pressing RESET & STOP. Pressing RUN causes the RUN signal go high, and then pressing STOP makes the RUN signal go low, so that is also OK.

The PRDY signal is always high. It looks like it should only go high when the RUN/STOP flip-flop is in the RUN state, or you do a Single Step, Examine, or Deposit. We looked at the output of the SN7430 IC O. The output is high, which indicates that one of the inputs is low (active). I can set the state of the RUN* signal on pin 12 high by pressing the STOP switch. Pin 11, SS* is high. Pin 5, EXM NNX* is high. Pin 6, EXM* is low (active). The EXM* signal should be high except when the EXAMINE switch is pressed. IC V pin 10 output is low, and pin 11 input is high so that IC is probably OK. The EXM signals on IC U pin 6 output is high (active), and pin 4 input is low, and pin 5 input is kind of low, about 1.5V. The kind of low signal needs to be investigated. The SN7473 (the schematic says SN74L73) IC J pin 8 output is 1.5V, and pin 9 is low. Pin 8 should be at +5V if pin 9 is low, so this IC is likely bad.


We replaced IC J with a NOS part, and while we were soldering we replaced the toggle switch for address bit-12 with a spare that came with Altair #1. Now the CPU will halt and run when the STOP or RUN switch is pressed.

EXAMINE looks like it is doing an EXAMINE NEXT, and it is not loading the address switched. DEPOSIT is doing something, but needs further investigation.

8/15/20

Time to find out why we can't EXAMINE or DEPOSIT.

The signal from the EXAMINE switch goes into the SN74123 Retrigerable Monostable Multivibrator IC L to get debounced, and then goes into SN7473 JK Flip-Flop IC J which is wired as a 2-bit counter. The signal on the SN7402 IC R pin 6 looked OK, so the switch and the debounce circuit is working OK.

We connected the 'scope to pins 12, 13, 9 & 8 on IC J so we can see if the 2-bit counter is going through the EXAMINE steps. After pressing the EXAMINE switch we can see the counter go through the four step sequence for an EXAMINE. These counter outputs control the Processor Ready (PRDY) signal on the backplane, and gate signals on the databus to make the processor chip perform a JMP instruction to the address contained in the switches.

We looked at outputs of IC U & T and IC A, B, C, D and E to see if the JMP instruction and switch addresses were getting onto the databus. First we see IC T pin 6 go low, then IC W pin 10 go low, then pins 4 & 6 of IC C and pins 4 & 2 of IC D go low. These are the bits for the JMP instruction. Then IC U pin 11 goes high which gates the lower 8 switches onto the databus, then IC U pin 8 goes high which gates the upper 8 switches onto the databus, then PRDY is driven low to stop the CPU. Those signals all looked OK. We noticed that IC W pin 2 was also active when the EXAMINE switch is pressed and was driving all of the data lines low when only the bits for the JMP instruction should have been driven low. This signal should only be active when EXAMINE NEXT is pressed. IC U pin 3 was active when EXAMINE is pressed. IC U pin 2 has signals on it when EXAMINE is pressed, but the low signal (EXM NXT) on IC U pin 1 should have prevented the signals on pin 2 from propagating to pin 3. We replaced IC U, the SN7400, with a new part, and now we can EXAMINE, EXAMINE NEXT. DEPOSIT, and DEPOSIT NEXT.

We were able to toggle in a little program and run it, and single-step the CPU. It looks like the front panel is fully functional.

We connected the Micropolis floppy diskette drive cable to the Micropolis Floppy Diskette Controller, inserted a 16-sector hard-sectored floppy diskette, set the address switches to 0xF400, pressed RESET, EXAMINE, and then RUN. This runs the floppy diskette bootloader stored on the diskette controller. The head loaded with a clunk and the drive select LED turned on. We could see activity on the front panel LEDs as it tried to boot from an empty diskette. We connected laptop running a terminal emulator to SIO port 1, but could not see anything on the terminal.

We toggled in a 2SIO echo program, but could not get anything to echo on the terminal emulator. We single-stepped the program and it looks like there is always a character in the receive buffer. We will need to do some debugging on the 2SIO board next Saturday.

We should also toggle in and run a RAM test program to make sure the RAM board is OK.

8/22/20

Last week we fixed the front panel and did some initial testing on the CPU and RAM. We even tried the floppy controller to see if it would try to boot. It tried, but the floppy diskette was blank so it didn't get far. Once we get the serial console port working we can download a program that will copy a diskette image from a laptop to the floppy drive.

We studied the schematics of the 2SIO board looking for how the RS-232 signals are wired to the rear DB-25 connectors on the back of the chassis. We connected a DB-9 to DB-25 cable from a laptop to the Altair, and looked to see where the transmit data from the PC showed up. The transmit and receive signals were reversed so we had to insert a null-modem between the Altair and the laptop to get the RS-232 signals in the right place.

We toggled in the 2SIO loopback program from Mike Douglas and ran it. It looks like it is behaving the same as last week where it thinks that there is always a character in the input buffer. Single-stepping the loopback program shows that all of the bits in the 6850 ACIA are on. This should not be true.

We used the 'scope to verify that the address configuration on the 2SIO is correct. Pin 3 on IC P goes low when an IN or OUT instruction is executed which drives pin 9 (CS2*) of the 6850 ACIA. Pin 10 on IC T goes high and low when the program is single stepped which drives pin 11 (RS) of the 6850 ACIA. Pin 12 of IC S goes low when an OUT instruction is executed, which drives the pin 13 (R/W) of the 6850 ACIA.

We can see pin 1 (1CLK) of IC V, the SN7473, go low when the I/O address matches and then pin 13 (1Q*) of IC V goes low. This puts the CPU in a Wait state for 500 ns. Then the PWAIT backplane signal goes high, gets inverted by IC U, and drives pin 2 (CLR) of IC V low, which clears the flip-flop and drives pin 13 (1Q*) of IC V high, which releases the PRDY signal on the backplane.

The signal from pin 8 of IC P is going low to enable the bus driver chip IC A. We looked at the signals on pins 11 & 12, and 13 & 14 of chip A, the SN74367 bus driver . It looks like the data signals from the 6850 ACIA chip are not being driven onto the backplane. The input signals to IC A, that are the data from the 6850 ACIA, are at 2V, so it is in an indeterminate state and the data read from the 6850 ACIA shows up as all ones.

We swapped the two 6850 ACIA ICs, but it didn't change the behavior of the data signals.

8/29/20

Last week we tested all of the logic that is used to decode the I/O address on the S-100 bus, and the logic that selects one of two 6850 ACIA on the 2-SIO board, and which register in the ACIA is the target of the I/O instruction. All of that seemed to be working OK.

We checked the transmit/receive clock frequency. It is running at 19200 KHz. When the ACIA divides this by 16 it will be configured for 1200 baud.

During a IN instruction that reads the Status Register in the ACIA it looks like the ACIA is not driving the local data bus that gets driven onto the S-100 bus. I think that it is unlikely that both of the ACIAs are defective, so we will look at the signals that cause the ACIA to do something.

ACIA Selection Signals

  • RegisterSelect (pin 11), connected to A0 on the backplane

  • ChipSelect0 (pin 8) , tied to +5V so it is always active

  • ChipSelect1 (pin 10), connect to A1 on the backplane, inverted for ACIA 1, not inverted for ACIA 2