DEC PDP-9 Restoration

12/22/12

We removed the 709 power supply and checked for physical damage. Everything looked OK.

We reformed all of the capacitors in the power supply because it had not been powered on in a long time.

This is a process were a power supply is voltage limited to a little less than the rated voltage of the capacitors

and is current limited to about 20mA is connected to the capacitors. The voltage on the capacitors will build to

the set voltage over several minutes. Once this is completed the oxide insulating layer is rebuilt in the capacitors

and the will work OK. If you just turn on the power supply you will likely damage the capacitors.

We also reformed the electrolytic capacitors on the boards in the core memory system.

Click on the image for a larger view.

We used a power supply current limited to 20mA to reform the capacitors.

We attached a resistive load to the power supply and measured the output voltages. All looked OK.

The fan was sticky so we sprayed some WD40 in the end bearing to free it up.

It is noisy, but it works OK a few seconds after it is powered on.

Eventually we will need to disassemble the fans and lubricate them with oil.

We reinstalled the power supply and connected the AC wires.

We connected 110VAC to the power cord to the 841A power controller.

We could control the power state with the power switch on the console.

We connected the remaining red/white AC wires to the 709 power supply and found that all of the chassis fans work OK.

Some of the fans are noisy so may have to disassemble all of the fans to lubricate them with machine oil.

1/19/13 update: I was able to buy two NOS Howard fans on eBay. They have the same motor, but difference fan blades.

We can probably transfer the blades from a worn out PDP-9 fan to one of the new motors.

Click on the image for a larger view.

It looks like the distance between the mounting holes is 4-1/8".

Click in the image for a larger view.

A close-up of the fan motor.

The second 709 power supply is missing the fan. Let us know if you have a source for replacements.

The hour meter runs and we add a few tenths of an hour to the 40,163 hours already on the system.

That is 20 years of 8 hours per day of run time.

We connected the DC wires to the 709 power supply.

It looks like the system was designed to have two of the 709 power supplies.

The connections to the other non-installed power supply are jumpered.

We turned the power supply on for a few seconds at a time and measured the voltages on the chassis test points.

The voltages looked OK and some lights on the console turned on.

We didn't smell anything burning and left the power on.

Warren measured the temperature of the modules in the system and found just a few above the ambient temperature.

Click on the image for a larger view.

We tried the basic Examine/Deposit functions, but did not get the expected response.

We can turn the PRGM STOP light on and off with the I/O RESET and START switches.

With the REGISTER DISPLAY switch in the API position the REGISTER lights flicker.

The rate of the flicker can be controlled with the REPEAT SPEED switch.

We connected the AC power to the paper tape reader/punch.

The punch motor didn't turn on with the AC power to the system.

We need to check the power switch on the front of the punch.

It looks like reader/punch has been modified and gets some of it's power through

additional wires, and some through the signal ribbon cable.

We will need to investigate this further.

Later this week we will do some basic debugging to see if any of the processor is working as expected.

12/28/12

We explored the Margin Power Supply control panel today because the voltage gauge was not working.

We found that the contacts in the wafer switch were really dirty.

We disassembled the switch, cleaned the contacts, and reassembled everything.

Of course our efforts didn't fix the voltage gauge.

Click on the image for a larger view.

The rear of the dissasembled Maintenance Panel.

Click on the image for a larger view.

One of the maintenance switch wafers before cleaning.

We traced the connections from the voltage gauge, through the wafer switch, and through the wiring harness.

The margin voltage sense wires terminated in a 2x3 contact connector mounted to a metal panel.

It turns out that the margin voltage sense wires get daisy chained from the CPU, to the TC59, to the TU20.

There was a cable to interconnect the margin bus from the TC59 to the TU20.

The "out" connector in the TU20 had a "loopback" plug plugged in.

We can't find the margin sense harness that goes from the CPU to the TC59. We should have it somewhere.

We plugged the loopback plug into the CPU margin connector and now the margin voltage gauge works.

At the same time we looked for the I/O bus cable that goes from the CPU to the TC59.

We should have it, but it is missing somewhere in the warehouse right now.

We repaired two of the partially delaminated flexprint cables for the front panel.

We need to replace one flexprint with some ribbon cable so the rest of the lights on the front panel will work.

We connected the I/O cables and DC power cables to the paper tape reader/punch.

The punch motor runs when you push the feed switch.

The capstan for the punch does not advance because it is binding.

We need to disassemble the punch to clean and lubricate it.

The reader does not advance when you push the feed switch.

That will need some debugging because the controller actually controls the stepper motor.

12/29/12

Decided to look at why the Program Stop switch does not turn on the PRGM STOP light.

See page D-BS-KC09-A-10 Clock, Run, and Display (Sheet 1).

The PWR OK\ signal on pin L, and the CLK signal on pin D of the R409 in slot J22 look OK. (section D7 on the schematic)

The PWR OK\ goes active 150mS before the -15V is in regulation.

The CLK POS signal from pin F of the S603 in slot J23 is active when the RUN flip-flop in slot J31 is on. (section D6 on the schematic)

The KSP (Key Stop) signal going into the D pin of the R111 in slot J27 is active when the STOP key is pressed. (section C3 on the schematic)

The buffered KSP (Key Stop) signal going into the S pin of the R111 in slot J28 is active (-4V) when the STOP key is pressed. (section C3 on the schematic)

The R pin of the R111 in slot J28 is 0V. (section C3 on the schematic)

The L pin of the R111 in slot J28 is 0V.

The DONE(1) sognal on the K pin of the R111 in slot J28 is 0V. This indicates that the core memory cycle is not done.

The RUN(0) sognal on the N pin of the R111 in slot J28 is 0V when the processor is not running.

It turns out that the instruction didn't finish execution, so DONE(1) is not active, so the Program Stop switch is not enabled.

The I/O RESTART signal on pin D of the R002 in slot F34 is always low.

The CM CLOCK signal on pin U of the B105 in slot H22 is active.

The CLK POS signal on pins D & F of the R002 in slot J34 is active when the processor is running. (1MHz)(section C5 on the schematic)

The CM CLK signal on pin N of the B602 in slot H33 is active when the processor is running. (1MHz)(section C5 on the schematic)

See page D-BS-KC09-A-16 CM Timing.

The CM CLK signal on pin R of the R111 in slot E22 is active. (section C5 on the schematic)

The SM(1) signal on pin S of the R111 in slot E22 is high, so the CM CLK signal will not get to pin U.

The AM SYNC BUS(0) signal on pin P of the R002 in slot E21 is low (-4V).

12/30/12

We looked at the signals that select addresses in the Control Memory.

Since the processor is not running we set the Maintenance Panel in Deposit and turned repeat on.

Speed = 4 = 150 uSec repeat rate.

Maintenance = Examine.

Repeat = On.

See page D-BS-KC09-A-16 CM Timing.

The signals IN CLR and CLR are active (high) when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

The signals CM STROBE A, B, C, & D are all active. (section D3 & D2 on the schematic)

We found that the CM CURRENT signal was two 50ns pulses where it should have been a single 80ns +25ns/-0ns pulse. (section C2 on the schematic)

The pulses coming from the B105 module in slot F28 (section B3 on the schematic) looked OK.

The pulse from the B105 module is wire-Ored with the 25ns delayed pulse from the B310 module in slot EF29.

So, the B310 delay module is about 12ns slow and the two pulses are not merged.

Click on the image for a larger view.

The upper trace is the CM CURRENT signal (broken). The lower trace is the EAE STROBE DLYD signal.

We replaced the B310 with a spare module and now the CM CURRENT pulse is about 85ns. This is OK.

These signals are inverted.

Click on the image for a larger view.

The upper trace is the CM CURRENT signal (working). The lower trace is the EAE STROBE DLYD signal.

These signals are inverted.

See page D-BS-KC09-A-17 CM Addressing.

We looked at the CMP 0-3 & CMG 0-3 signals. (section D5 & D6 on the schematic)

There is what looks like a voltage as a result of the CM current pulse on all of these signals.

We thought that maybe there were shorted diodes on the G210 that would enable all of the outputs.

All of the diodes on the G210 tested OK.

The input and output signals on pins D & E of the B105 in slot H21 were complementary.

Next Saturday we need to determine if only one CM line is being activated.

We also need to see if the CM address starts at 0, then goes to 1, then to the rest of the Deposit cycle.

01/05/13

See page D-BS-KC09-A-16 CM Timing

We looked at the CM CURRENT signal in section C2.

The signal went low when when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

See page D-BS-KC09-A-19 CM Sense Flip-Flops (Sheet 1)

We looked at the 0->CMA signal in section C7.

It goes low at power up or when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

The PK CLR signal in section