DEC PDP-9 Restoration

12/22/12

We removed the 709 power supply and checked for physical damage. Everything looked OK.

We reformed all of the capacitors in the power supply because it had not been powered on in a long time.

This is a process were a power supply is voltage limited to a little less than the rated voltage of the capacitors

and is current limited to about 20mA is connected to the capacitors. The voltage on the capacitors will build to

the set voltage over several minutes. Once this is completed the oxide insulating layer is rebuilt in the capacitors

and the will work OK. If you just turn on the power supply you will likely damage the capacitors.

We also reformed the electrolytic capacitors on the boards in the core memory system.

Click on the image for a larger view.

We used a power supply current limited to 20mA to reform the capacitors.

We attached a resistive load to the power supply and measured the output voltages. All looked OK.

The fan was sticky so we sprayed some WD40 in the end bearing to free it up.

It is noisy, but it works OK a few seconds after it is powered on.

Eventually we will need to disassemble the fans and lubricate them with oil.

We reinstalled the power supply and connected the AC wires.

We connected 110VAC to the power cord to the 841A power controller.

We could control the power state with the power switch on the console.

We connected the remaining red/white AC wires to the 709 power supply and found that all of the chassis fans work OK.

Some of the fans are noisy so may have to disassemble all of the fans to lubricate them with machine oil.

1/19/13 update: I was able to buy two NOS Howard fans on eBay. They have the same motor, but difference fan blades.

We can probably transfer the blades from a worn out PDP-9 fan to one of the new motors.

Click on the image for a larger view.

It looks like the distance between the mounting holes is 4-1/8".

Click in the image for a larger view.

A close-up of the fan motor.

The second 709 power supply is missing the fan. Let us know if you have a source for replacements.

The hour meter runs and we add a few tenths of an hour to the 40,163 hours already on the system.

That is 20 years of 8 hours per day of run time.

We connected the DC wires to the 709 power supply.

It looks like the system was designed to have two of the 709 power supplies.

The connections to the other non-installed power supply are jumpered.

We turned the power supply on for a few seconds at a time and measured the voltages on the chassis test points.

The voltages looked OK and some lights on the console turned on.

We didn't smell anything burning and left the power on.

Warren measured the temperature of the modules in the system and found just a few above the ambient temperature.

Click on the image for a larger view.

We tried the basic Examine/Deposit functions, but did not get the expected response.

We can turn the PRGM STOP light on and off with the I/O RESET and START switches.

With the REGISTER DISPLAY switch in the API position the REGISTER lights flicker.

The rate of the flicker can be controlled with the REPEAT SPEED switch.

We connected the AC power to the paper tape reader/punch.

The punch motor didn't turn on with the AC power to the system.

We need to check the power switch on the front of the punch.

It looks like reader/punch has been modified and gets some of it's power through

additional wires, and some through the signal ribbon cable.

We will need to investigate this further.

Later this week we will do some basic debugging to see if any of the processor is working as expected.

12/28/12

We explored the Margin Power Supply control panel today because the voltage gauge was not working.

We found that the contacts in the wafer switch were really dirty.

We disassembled the switch, cleaned the contacts, and reassembled everything.

Of course our efforts didn't fix the voltage gauge.

Click on the image for a larger view.

The rear of the dissasembled Maintenance Panel.

Click on the image for a larger view.

One of the maintenance switch wafers before cleaning.

We traced the connections from the voltage gauge, through the wafer switch, and through the wiring harness.

The margin voltage sense wires terminated in a 2x3 contact connector mounted to a metal panel.

It turns out that the margin voltage sense wires get daisy chained from the CPU, to the TC59, to the TU20.

There was a cable to interconnect the margin bus from the TC59 to the TU20.

The "out" connector in the TU20 had a "loopback" plug plugged in.

We can't find the margin sense harness that goes from the CPU to the TC59. We should have it somewhere.

We plugged the loopback plug into the CPU margin connector and now the margin voltage gauge works.

At the same time we looked for the I/O bus cable that goes from the CPU to the TC59.

We should have it, but it is missing somewhere in the warehouse right now.

We repaired two of the partially delaminated flexprint cables for the front panel.

We need to replace one flexprint with some ribbon cable so the rest of the lights on the front panel will work.

We connected the I/O cables and DC power cables to the paper tape reader/punch.

The punch motor runs when you push the feed switch.

The capstan for the punch does not advance because it is binding.

We need to disassemble the punch to clean and lubricate it.

The reader does not advance when you push the feed switch.

That will need some debugging because the controller actually controls the stepper motor.

12/29/12

Decided to look at why the Program Stop switch does not turn on the PRGM STOP light.

See page D-BS-KC09-A-10 Clock, Run, and Display (Sheet 1).

The PWR OK\ signal on pin L, and the CLK signal on pin D of the R409 in slot J22 look OK. (section D7 on the schematic)

The PWR OK\ goes active 150mS before the -15V is in regulation.

The CLK POS signal from pin F of the S603 in slot J23 is active when the RUN flip-flop in slot J31 is on. (section D6 on the schematic)

The KSP (Key Stop) signal going into the D pin of the R111 in slot J27 is active when the STOP key is pressed. (section C3 on the schematic)

The buffered KSP (Key Stop) signal going into the S pin of the R111 in slot J28 is active (-4V) when the STOP key is pressed. (section C3 on the schematic)

The R pin of the R111 in slot J28 is 0V. (section C3 on the schematic)

The L pin of the R111 in slot J28 is 0V.

The DONE(1) sognal on the K pin of the R111 in slot J28 is 0V. This indicates that the core memory cycle is not done.

The RUN(0) sognal on the N pin of the R111 in slot J28 is 0V when the processor is not running.

It turns out that the instruction didn't finish execution, so DONE(1) is not active, so the Program Stop switch is not enabled.

The I/O RESTART signal on pin D of the R002 in slot F34 is always low.

The CM CLOCK signal on pin U of the B105 in slot H22 is active.

The CLK POS signal on pins D & F of the R002 in slot J34 is active when the processor is running. (1MHz)(section C5 on the schematic)

The CM CLK signal on pin N of the B602 in slot H33 is active when the processor is running. (1MHz)(section C5 on the schematic)

See page D-BS-KC09-A-16 CM Timing.

The CM CLK signal on pin R of the R111 in slot E22 is active. (section C5 on the schematic)

The SM(1) signal on pin S of the R111 in slot E22 is high, so the CM CLK signal will not get to pin U.

The AM SYNC BUS(0) signal on pin P of the R002 in slot E21 is low (-4V).

12/30/12

We looked at the signals that select addresses in the Control Memory.

Since the processor is not running we set the Maintenance Panel in Deposit and turned repeat on.

Speed = 4 = 150 uSec repeat rate.

Maintenance = Examine.

Repeat = On.

See page D-BS-KC09-A-16 CM Timing.

The signals IN CLR and CLR are active (high) when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

The signals CM STROBE A, B, C, & D are all active. (section D3 & D2 on the schematic)

We found that the CM CURRENT signal was two 50ns pulses where it should have been a single 80ns +25ns/-0ns pulse. (section C2 on the schematic)

The pulses coming from the B105 module in slot F28 (section B3 on the schematic) looked OK.

The pulse from the B105 module is wire-Ored with the 25ns delayed pulse from the B310 module in slot EF29.

So, the B310 delay module is about 12ns slow and the two pulses are not merged.

Click on the image for a larger view.

The upper trace is the CM CURRENT signal (broken). The lower trace is the EAE STROBE DLYD signal.

We replaced the B310 with a spare module and now the CM CURRENT pulse is about 85ns. This is OK.

These signals are inverted.

Click on the image for a larger view.

The upper trace is the CM CURRENT signal (working). The lower trace is the EAE STROBE DLYD signal.

These signals are inverted.

See page D-BS-KC09-A-17 CM Addressing.

We looked at the CMP 0-3 & CMG 0-3 signals. (section D5 & D6 on the schematic)

There is what looks like a voltage as a result of the CM current pulse on all of these signals.

We thought that maybe there were shorted diodes on the G210 that would enable all of the outputs.

All of the diodes on the G210 tested OK.

The input and output signals on pins D & E of the B105 in slot H21 were complementary.

Next Saturday we need to determine if only one CM line is being activated.

We also need to see if the CM address starts at 0, then goes to 1, then to the rest of the Deposit cycle.

01/05/13

See page D-BS-KC09-A-16 CM Timing

We looked at the CM CURRENT signal in section C2.

The signal went low when when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

See page D-BS-KC09-A-19 CM Sense Flip-Flops (Sheet 1)

We looked at the 0->CMA signal in section C7.

It goes low at power up or when the Deposit, Deposit Next, Examine, Examine Next, and I/O Reset keys are pressed.

The PK CLR signal in section C5 has the same behavior.

We looked at the 0 and 1 outputs of the CMA 0 Flip-Flop in section C6.

Both outputs were at ground level.

There was no -15V on the B pin of the module.

We eventually traced the problem to a dirty 04 margin switch.

When the -15 was restored to the Flip-Flop it worked correctly.

With the CM sense Flip-Flops working we started seeing some signs of life in the system.

The address set in the switches gets copied to the ADR register when the EXAMINE switch is pressed.

A lot of the system has to be functional for this to happen.

When the system is powered on all of the CM Sense Flip-Flops are cleared by the 0->CMA and PK CLR pulses.

When the EXAMINE switch is pressed the KIOA signals are set to 3.

When the CM CURRENT signal is activated the CM data at location 01 is read.

The CM STROBE * signals latch this data into the CM Sense Flip-Flops.

The ADSO, MBI, and SM bits in the CM data are set so the Address Switch contents are gated to the I/O Bus (B).

Then Address Switch contents are gated to the O Bus, and then to the AR Register and the MB register.

The next CM address from the contents of 01 is 25.

The CM content turns on MBO, ARI, and KEY.

This copies the contents of the MB register to the AR register.

At this point the MC hangs waiting for the Memory Read Strobe.

The behavior of the MC is not consistent and is affected by the Speed switch setting.

Next week we will connect a logic analyzer to the CM Flip-Flops to make sure that everything is working correctly.

We also need to determine why the CM is not getting a response from the Core Memory Controller.

01/12/13

The Mode Info flexprint cable #26 that goes from the front panel to slot CP H36 had peeled apart.

I replaced the flexprint with modern ribbon cable because the signals in the cable are static.

The SING STEP, SING INST, and REPT lights work now.

We ran the maintenance test described in section 3.7.7.3 of the PDP-9 maintenance manual.

To start the diag you press the I/O RESET switch, turn the console REPT switch on, set the maintenance switch in the MAINT position, and latch the START switch up.

The contents of the AR register are copied to all of the other registers. You can use the REGISTER DISPLAY switch to see the contents of the registers.

The contents of the AR go onto the A bus, are run through the ADR to increment the value, and then onto the O bus, and into the MB.

The contents of the MB go onto the B bus, the B bus goes through the ADR, and onto the O bus.

The O bus is loaded into the AC, AR, and PC registers. It would also go into the MQ register if this system had the EAE.

The contents of the address switch register can also be inclusive-ORed with the ADR.

All of this behavior looks OK, so that means that large parts of this system are functional, especially the Control Memory.

See page D-BS-KC09-A-10 CM Clock, Run, and Display (Sheet 1).

We looked at the A, B, and C flip-flops in section D2 & D3 because they control much of the CP timing.

The REPT CLK period is 8 uS, 28 uS, 200 uS, 2.6 mS, and 80 mS for switch settings of 5-1.

This is close to the values in the table on page D-BS-KC09-A-10 CM Clock, Run, and Display Timing.

Click on the image for a larger view.

The top trace is the REPT CLK. The bottom trace is the flip-flop C(0) output on pin J.

The period of the REPT CLK is 200 uS so the REPT SPEED switch was set to position 3.

This looks OK, and was also OK at other speed settings.

There was no output on pin J when the processor was running. This is OK.

Click on the image for a larger view.

The top trace is the flip-flop C(0) output on pin N of flip-flop B.

The bottom trace is the flip-flop B(0) output on pin P.

The period of the C(0) is about 18 uS so the REPT SPEED switch was set to position 5.

The output of the B flip-flop has glitches when the input signals change.

We swapped the S206 modules in slots J29 & J30. There was no change in the behavior.

We need to fix this or the CP timing will be really confused.

The Hours Meter showed 40181.9 when we finished.

01/19/13

EXAMINE and DEPOSIT are not working.

We need to determine if this is a processor or memory problem.

We spent some more time looking at the system's behavior when it is doing an EXAMINE.

We are actually getting three CM CURRENT pulses, not just two as we originally though.

One was 5uS before the other two when were running in a slow speed, so we didn't see it on the 'scope.

The first CM word has the SM bit turned on so it will wait to synchronize with the core memory controller timing.

The second and third words run asynchronously with the core memory controller.

Click on the image for a larger view.

The top trace is RUN.

The bottom trace is CM CURRENT.

The first CM CURRENT pulse should be reading CM word 01.

The second pulse should be reading CM word 25.

The third pulse should be reading CM word 26.

We looked at all of the CP/Memory Interface signals on page D-BS-KC09-A-24 CP/Memory Interface.

All of the signals looked reasonable, so the core memory controller is alive.

We didn't see any data from the sense amps.

It is possible that we have written all ones to all core locations with our experiments.

Click on the image for a larger view.

We looked at all of the signals on page D-BS-KC09-A-29 System Timing.

Everything here looks OK.

The IO RESTART signal was static so it was not included.

We spent some time looking at the schematics trying to determine the difference between the Examine and Deposit behavior.

From the schematics it is not obvious.

01/26/13

We looked at the D-BS-KC09-A-19 CM Sense Flip-Flops (Sheet 3) to see if the SAO flip-flip is working correctly.

We were thinking that if the SAO signal was always off the processor would always do a DEPOSIT cycle and never read core.

Click on the image for a larger view.

The top trace is RUN.

The bottom trace is SAO(1) for an EXAMINE cycle.

Click on the image for a larger view.

The top trace is RUN.

The bottom trace is SAO(1) for a DEPOSIT cycle.

So, it looks like the SAO signal is active and is different for an EXAMINE and DEPOSIT cycle.

Now that we know that the signal is active we need to verify that the timing is OK.

We decided to look again at the behavior of the A/B/C flip-flops on page D-BS-KC09-A-10 CM Clock, Run, and Display Timing.

We also looked at the timing diagram on page D-BS-KC09-A-11 CM Clock, Run, and Display Timing.

Click on the image for a larger view.

The top trace is RUN.

The bottom trace is C(1) for a repeated EXAMINE cycle.

We noted on 01/12/13 that the B flip-flop had glitches on the output and was not doing a divide-by-two.

Click on the image for a larger view.

The top trace is RUN.

The bottom trace is B(1) for a repeated EXAMINE cycle.

Since RUN(1) is tied to the preset input of the B flip-flop the B(1) output gets forced back high when it tries to flip low.

So this is normal behavior after all.

02/02/13

We decided to look at the operation of the core memory controller today.

With the system in maintenance mode performing repeated deposits we can see the address switches moving to the MB and then to the AR.

We can see the data switches moving to the MB.

A large part of the system needs to be functional for just that to work.

See page D-BS-MC70-B-11, Memory Test Connections.

We looked at all of the core memory signals available on the test connectors.

All of the signals are active, have reasonable wave forms, and reasonable timing.

Click on the image for a larger view.

These traces show the read and write current going through the current limiting resistors.

See page D-BS-MC70-B-4, Digit Drive Bits 0-17 (Sheet 1).

All of the address and data signals used for bit 0 look OK in their high and low states.

The Digit Write Sink (1) signal is 800 ns after the CLK signal. That looks reasonable.

The +V Digit 00 Res and -V Digit 00 Res signals look OK for all 16 possible memory address combinations, and for read and write.

That means that all of the steering diodes, drive transistors, and core wiring is OK.

The MBS00 through MBS17 signals all look OK in their high and low states.

That means that the data switches are getting to the core.

See page D-BS-MC70-B-5, Word Selection.

All of the address signals look OK in their high and low states.

The WR ^ MA5(1) and the WR ^ MA5(0) signals look OK and occur 800 ns after the CLK. Looks OK.

The WW ^ MA5(0) and the WW ^ MA5(1) signals are just high. There is no WORD READ strobe.

This would prevent the core from being read.

Click on the image for a larger view.

The top traces are 100 ns/division.

The bottom two traces are 200 ns/division.

See page D-BS-MC70-B-1, Memory Control (Sheet 1).

The MA5(0) and MA591) signals look OK.

The WORD WRITE(1) signal looks OK.

The WORD READ(1) signal is just high.

So the problem is not with these inverters.

See page D-BS-MC70-B-1, Memory Control (Sheet 2).

The READS OFF and WORD READ ON signals look OK and the timing looks reasonable.

The WORD READ(0) signal look OK, but the WORD READ(1) signal is just high.

We replaced the B213 flip-flop module in slot H33 with a spare.

Now we can read the original contents of core memory, but it is not rewritten.

We cannot deposit to core.

This is some real progress!

We looked at the outputs of the rest of the flip-flops on this schematic page.

All look OK except that DIGIT WRITE SINK(1) only goes down to -3V and the rest go to -4V.

We replaced the B213 in slot B16 with a spare, but it did not change the signal shape.

This signal goes to all 18 G219 Memory Selector modules.

We pulled all of the G219 modules, replaced 2, and looked a the DIGIT WRITE SINK(1) signal.

The signal looked OK until we got to the G219 in slot AB09.

We replaced the G219 with a spare module and the DIGIT WRITE SINK(1) still looked OK.

We had hoped that the core would read and write now, but found that the data switches are not transferred to the MB.

Oh well, now we know what to look at next week.

The Hours Meter showed 40193.5 when we finished.

02/09/13

No work due to blizzard.

02/16/13

Just to make sure that the registers, microcode, I/O buses, etc were working OK we ran the build in maintenance test.

All the register contents looked OK so we continued debugging the core memory write problem.

On 2/2/13 we noticed that we could read core, but the rewrite or deposit did not work.

Warren scanned core addresses and found a location that has bit-7 on.

We looked at the B169 module in slot C31. See page D-BS-MC70-B-3, Memory Input Multiplexer.

Pin J was high indicating that the MB07(0) signal was present.

Pin F Mode(0) was low indicating that the processor was granted access to the core memory.

Pin D was low indicating that the MBS07 was present.

We looked at the MBS07 signal on the G219 modules in slots AB09 and EF09.

The signal was present on both. See page D-BS-MC70-B-4, Digit Drive Bits 0-17 (Sheet 4)

So at least we know that the bits that were read from core made it back to the Digit Drive modules.

We wanted to make sure that the data switches from the console made it to the Digit Drive modules and changed the current waveform.

See page D-BS-MC70-B-4, Digit Drive Bits 0-17 (Sheet 1).

We looked at the -V DIGIT RES 00 signal on pin FF of the G219 in slot EF07.

We could see a 20V pulse when the bit-0 data switch was on.

So now we have verified that the Digit Drive signals look OK.

That only provides 1/2 of the current needed to write core, so it was time to look at the Word Selectors.

Click on the image for a larger view.

The top trace is CLK.

The bottom trace is -V WORD RES.

See page D-BS-MC70-B-5, Word Selection.

We looked at the -V WORD RES signal on pin JF of the G219 module in slot HJ27.

The signal was a steady -30V. This should have a pulse on it that was similar to the -V DIGIT RES 00 signal.

Without this pulse the write current to the core will be 1/2 of the required current and it will not work.

We looked at the +V WORD RES signal on pin HH of the G219 module in slot HJ27.

We saw a -30V pulse similar to the +V DIGIT RES 00 signal.

Since the +V WORD RES signal looked OK we knew that all of the MA signals were OK.

We previously has a problem with the WR(1)^MA5(1) v WW(1)^MA05(0) signal that was caused by a faulty G219 module.

Click on the image for a larger view.

The top trace is CLK.

The bottom trace is WR(1)^MA5(0) v WW(1)^MA05(1).

We looked at the WR(1)^MA5(0) v WW(1)^MA05(1) signal on pin HV of the G219 in slot HJ27.

The pulse should have gone to -4V, but only went to -2V.

Since this signal only goes to the Word Drive G219 modules we pulled all eight of the modules associated with the Word Drive circuitry.

Without the G219s installed the WR(1)^MA5(0) v WW(1)^MA05(1) signal went to -4V so we knew that we had another defective G219 module.

After replacing the G219 modules one at a time we found that the one in slot HJ24 was the defective one.

After replacing the G219 with a spare the WR(1)^MA5(0) v WW(1)^MA05(1) signal went to -4V.

A quick test showed that we could examine, rewrite, and deposit to core.

This was a major milestone and meant that we could see if the processor would do anything.

We did some instruction testing to see what works.

The RAL, RAR, RTL, RTR, CLL, STL, CML, CLC, CLA, and CMA instructions work OK.

If the IZS instruction is not doing a skip it works OK. If the ISZ does a skip it sometimes goes to location 0.

The JMP instruction sometimes stores the contents of the PC where the JMP instruction was.

Well, the processor is alive, and lots of the instructions seem to work OK.

We will work on the flakeyness in the JMP and ISZ instructions next week.

Maybe connecting a logic analyzer to the ROPE memory sense amps would show if the microcode is working correctly.

02/23/13

Last week we found that the JMP and ISZ instructions were unreliable.

They worked OK when single stepping, or when running at a very low speed.

The processor would go off into the weeds when running at full speed.

This week we connected Warren's Logic Analyzer to the Control Memory address lines so we could see the micro-instruction flow while it was executing a JMP instruction.

It took a few tries to determine which signals and which polarity of the signals we needed to watch, but we eventually figured it out.

Click on the image for a larger view.

Warren's USB logic analyzer is the little silver box on the 'scope cart.

In conjunction with a digital 'scope we can really see what the processor is doing.

I can't imagine how a DEC field service person would have fixed the processor issues without a logic analyzer.

See schematic page D-FD-KC08-A-6 Key Flow and schematic page D-FD-KC08-A-18 CM Wiring Matrix and Program (Sheet 1)

It you push the IO RESET key the CM address lines would go to 01.

This confirms that the processor will just sit on the KEY NOP CM word.

When you press the EXAMINE key the processor goes to:

CM word 01 which copies the address switches to the MB, and starts a memory cycle.

CM word 25 which copies the address in the MB to the AR and is displayed on the console.

When the memory cycle finishes the contents of the core location will be in the MB and is displayed on the console.

CM word 26 which copies the PC to the MB in preparation for an EXAMINE NEXT.

We entered a JMP 000200 at address 000200 and ran it.

The processor would execute a few JMP instructions correctly and then execute the wrong micro-instructions.

When it failed the CM CURRENT strobe was about 1/2 of the expected duration.

Click on the image for a larger view.

The top trace is CM CURRENT.

The traces below are the CM address lines A1, A2, A3, A4, A5, and A6.

The address bits on the logic analyzer were grouped into a bus to make it easier to interpret. Unfortunately we got the bits in reverse order.

At the left the CM was left in the Fetch state, CM word 21, by the EXAMINE we had performed earlier.

The CM CURRENT strobe read CM word 6, the START key.

The next CM address in the cycle is 21, the FETCH state.

Click on the image for a larger view.

At the top left the CM CURRENT strobe finally happens after a long delay.

This is the FETCH state, CM word 21.

Then the CM word 12 is processed to decode the instruction.

The next CM address in the sequence is 24, but it is never used.

When the instruction is decoded it modifies the next address to CM word 74, the JMP.

Click on the image for a larger view.

Then we go to CM word 10, BGN.

Then we go to CM word 21 to fetch the next instruction.

Unfortunately the CM CURRENT strobe for the fetch is only 25ns long when it should be 70ns.

The next CM word 14 instead of 12 and then CM word 37 and the processor stops.

See schematic page D-FD-KC08-A-16 CM Timing.

The Control Memory Timing Circuit takes the output from pin D of the B602 Pulse Amplifier in slot F30, runs it through a B105 inverter in slot F28.

The output from the inverter goes to the B310 25ns delay line in slot EF29.

The output from the B105 inverter is wire-ORed with the output from the B310 delay line to stretch the 25ns signal into a 50ns signal.

When the processor fails the CM CURRENT strobe is only 25 ns long.

The short CM CURRENT signal does not put enough energy into the ROPE memory so it does not work correctly.

We think that the B130 delay line in slot EF29 that we replaced at the beginning of our debug efforts is defective.

The system behavior is better when it is cold, so maybe one of the transistors on the B130 is partially bad.

The two spare B130 delay lines that we tried were also broken.

We will repair two B130 modules this week and continue our work next week.

03/02/13

We bought some DEC3639 (2N3639) transistors from Circuit Specialists to repair the two defective B310 delay lines that are spares.

The D-664 diodes measured OK and we replaced all four transistors.

We also found lots of broken solder joints at the delay lines that probably were the cause of the problem in these spare boards.

See schematic page D-FD-KC08-A-16 CM Timing.

This week we added a lot more connections to the Logic Analyzer so we could see all of the signals that generate the CM CURRENT pulse.

The pulse that generates the CM CURRENT pulse for a fetch cycle starts with the CM CLK and SM(1) signals going to the R111 in slot E22.

This pulse is shorter than the pulse for the other types of processor cycles.

The schematic says that the CM CURRENT pulse needs to be 80 ns +25 ns / - 0ns.

The pulse from the fetch cycle is sometimes as short as 25 ns and sometimes there are two pulses.

The pulse that generates the CM CURRENT pulse for the other processor cycles comes from the B104 in slot F31.

These CM CURRENT pulses look OK.

We found that B310 delay line in slot EF29 had been change from the factory setting to reduce the delay by 12.5 ns.

The replacement wire-wrap was the wrong wire size, was not installed with the correct tool, and was loose and a poor connection.

Click on the image for a larger view.

The new wire from pins FN to FR was loose on the backplane pins so we replaced it with the factory setting from FN to FP.

If you look to the right of the 'scope probe you can see another timing jumper change from the factory setting.

Next week we will go through the process of measuring and adjusting the Control Memory circuit delays.

The processor is running reliably if we set the speed to 5 and lock the CONT switch on.

This runs the processor about 50 times slower than normal.

Hopefully adjusting the timing will let it run at the full 1 MHz speed.

Not bad for a 45 year old machine.

We tested a few more instructions and found that the LAC (Load Accumulator) and TAD (Twos Compliment Add) instructions work OK.

The DAC (Deposit Accumulator) instruction puts the contents of the AC back in memory, but then goes to the wrong address to execute the next instruction.

It looks like the contents of the AC is getting transferred to the PC.

That should not be too difficult to debug.

We also found that the ISZ (Increment and Skip if Zero) instruction does not increment the contents of a memory location.

03/10/13

Some of the delay settings in the CM timing circuit have been changed from the factory settings.

One changed wire was wire-wrapped correctly, so it may have been done at the factory or by DEC field service.

Two of the delay changes were a hack, and looked like the wires were just twisted around the wire-wrap post with pliers.

We removed these two wires and put them back to the locations shown in the schematic.

Click on the image for a larger view.

The system will now run at full speed!

We tried the LAW (Load AC with "n") instruction and it works OK. Only bits 5-17 can be used for the constant.

The ISZ is still broken. Fixing that should be our project for next week.

These are the original and the current settings for the B310 delay lines for the Control Memory.

See schematic page D-FD-KC08-A-16 CM Timing.

There is a chart at the top of this schematic page that lists a sequence for measuring and setting the Control Memory delays.

The first check is the delay from the CLK at C01H to the CM CURRENT at F26U. The delay should be 26ns +/- 10ns, and measured 50ns. This is a "check only" so we will look at this again later.

The second check is the delay from CLK at C01H to CM STROBE D at E27N. The delay should be 100ns +/- 10ns, and measured 96ns. We will leave this alone.

The third check is the width of CM CURRENT at F26U. The width should be 80ns + 25ns - 0ns, and measured 60ns. We will try to make this longer to get more current into the CM cores.

We tried replacing the R111 module at F26. There was no change to the width of CM CURRENT.

We tried replacing the R111 module at E24. There was no change to the width of CM CURRENT.

We thought that a bad diode on one of the G210 CM Driver modules could load the CM CURRENT signal.

We pulled both G210 modules, but without a load we couldn't see the CM CURRENT signal.

All of the diodes on the G210 measured OK.

We thought that a bad diode or resistor on the W005 at F27 might not pull down the CM CURRENT signal enough.

We tried two different W005 modules, but there was not change to the CM CURRENT signal.

The system runs at full speed now, so we will focus our efforts on getting all