DEC VAX 6000-410
This VAX 6000-410 system was connected to the VAX 8650, VAX 6000-510, VAX 7000, and disks on the HSC90 through the CI interface.
During January 2002 Merle Pierce drove to Wisconsin to retrieve several machines including this VAX 6000-510, donated by Gunter Schadow. This machine consists of a two CPUs with a Numonics performance enhancer, two BIbus Adapters, and BIbus I/O boards. The VAX was connected to a cluster controller and then to a cabinet containing eight RA90 disk drives.
The VAX 6000 Model 410, code-named "Calypso/XRP", was introduced on 11 July 1989. It used the KA64A CPU module and could be configured with one to six such modules for one to six processors. The KA64A contained a 35.71 MHz (28 ns cycle time) Rigel chip set with an external 128 KB B-cache (L2 cache). The B-cache was direct-mapped and used a 64-byte cache line size with a 16-byte sub-block size. It was constructed from twenty-four 64 KB (4-bit by 16,384-word) 15 ns SRAMs. The module also contained a REXMI chip set, whose purpose was to interface the Rigel chip set's DAL (data and address line) bus to the XCI ASIC, the user side of the XMI corner interface. The REXMI chip set was composed of the XCA controller/address chip and two XCP data path chips. The XCA and XCP were ASICs developed using a standard-cell methodology and fabricated in Digital's CMOS-2 process. The Rigel chip set's DAL (data and address line) bus was interfaced to the XMI corner (a section of a XMI module containing XMI bus logic) and then to the XMI bus by the REXMI interface. A maximum of 256 MB of ECC memory was supported.
BI Bus I/O boards from right to left.
The VAX 6000-410.
The VAX 6000-410 inside. The card cage at the middle right contains the CPUs and memory,
The card cage at the middle left contains the XMI I/O boards.
The VAX 6000-410 XMI CPU Card Cage. There are two CPUs at the left, five memory boards in the middle, and a BI interface at the right.
The VAX 6000-410 BI bus Card Cage.