PDP-11/40 #2
Restoration 2026

Back to the 2025 restoration blog.

1/3/26

• If we DEP and EXAM a register everything works OK. If we EXAM memory it works OK, but if we DEP memory the processor goes into space. We stepped through the DEP microcode starting at 034. When the microcode gets to step 072/030 it is doing the Unibus write. Instead of branching to step 030 it actually went to 336/317. Ashlin pointed out that these are the addresses of the TRAP ERR microcode.  The current thought is that when the Unibus write happened the memory board drove BUS PB L signal to report a memory parity error. It should never report a parity error on a memory write.

• Jumper W8 on the Status board disables the Parity Error Trap. It was installed on our Status board. For good measure we resoldered the jumper. Now we can DEP without problems.

• We toggled in Ashlin's counting program from: https://blog.tephra.me/pdp-11-40-test/ The PDP-11/40 is actually running its first program! Ashlin's Light Chaser program also runs.

• We started working on the M7800 DL11 serial port for the console. The crystal in ours is 4.608 MHz, so it will support 9600 baud. 9600 7E1 is probably the preferred console port configuration.

  • 777560 Receiver Status Register

  • 777562 Receiver Buffer Register

  • 777564 Transmitter Status Register

  • 777566 Transmitter Buffer Register

• We toggled in one of Ashlin's programs that sends a stream of As out the serial console. We connected a serial breakout box to the console cable and pin-3 RD data was constantly lit. We connected a VT220 terminal to the breakout box and when we typed on the keyboard pin-2 RD data lit. That means we didn't have a DTR-DSR configuration conflict and don't need a null-modem adapter. The VT22o displayed a stream of "P" characters. The program said that it would send a stream of "A" characters, so we have a problem. We tried other characters, and they worked OK. We went back to the "A" character and it worked.

• The M9312 bootstrap terminator board has a Console Emulator ROM as well as a few Bootstrap ROMs. 

  • The Console Emulator starting address is 165020

• Starting the Console Emulator at the normal address results in the processor halting at 165052. When it halted the Z & C indicators were on and R3 was zeros.

• Pressing CONT resulted in a halt at 165466. 

• The Console Emulator ROM matches this listing

  •       165020 005003               T1: clr r3 ; R3=000000 C=0

  •       165022 005203                  inc r3 ; R3=000001 C=0

  •       165024 005103                  com r3 ; R3=177776 C=1

  •       165026 006203                  asr r3 ; R3=177777 C=0

  •       165030 006303                  asl r3 ; R3=177776 C=1

  •       165032 006003                  ror r3 ; R3=177777 C=0

  •       165034 005703                  tst r3 ; R3=177777 C=0

  •       165036 005403                  neg r3 ; R3=000001 C=1

  •       165040 005303                  dec r3 ; R3=000000 C=1

  •       165042 005603                  sbc r3 ; R3=177777 C=1

  •       165044 006103                  rol r3 ; R3=177777 C=1

  •       165046 005503                  adc r3 ; R3=000000 C=1

  •       165050 000303                  swab r3 ; R3=000000 C=0

  •       165052 001377                  bne . ; br . if FAIL

• We single-steeped through the register test code and found that SWAB instruction causes a HLT. We ran the rest of the Console Emulator ROM and each SWAB instruction caused a HLT. Time to step through the SWAB microcode to see what it does.

• We executed a SWAB instruction (000303) and stopped the microcode with a match at address 016. The microcode address sequence then was 001, 004, 005, 122. It looks like it is interpreting a SWAB as a HALT. Probably another problem in the IR Decode board.

• We looked at the K3-5 BUBC0(BUT37) H, K3-5 BUBC1(BUT37) H, K3-5 BUBC2(BUT37) H, and K3-5 BUBC3(BUT37) H signals on the IR Decode board with the 'scope. We entered a bunch of SWAP R0 instructions and pointed the PC to them. We pressed START, stopped the microcode at 032, and stepped the microcode through START until it got to 004/005. The BUBC0..BUBC3 signals were all high. The next microcode step went to 137.

• We looked at pin 8 of E52 on the IR Decode board. It was high, so that would make the microcode branch to the wrong address. We looked at the inputs and found that pins 1 & 2 were high, so there is a problem. We looked at pin 8 of E66 (the one that we replaced Wednesday), and it was high. We looked at the inputs on E66 and found pin 13 was low. That is signal K5-3 FALSE BR L from the Status board.

1/4/26

• We setup the 'scope to look at E90 on the Status board, the source of the K5-3 FALSE BR L signal. We put a SWAB instruction in memory at 1000, put 1000 in the PC, set the KM11 MSTOP switch on, and set the console switches to stop at microword 005. When we pressed START with the ENABLE switch on, the microcode stopped at address 005, just where it is decoding the instruction. 

• It looks like we have multiple problems. The next microcode address is 113, where it should be 134 for a SWAB instruction. It is now not decoding some instructions correctly. We reentered Ashlin's counting program, and it ran OK. At least the processor is decoding CLR, INC, and BR instructions correctly.

• We also see pin-1 high, pin-2 low, and pin-3 high on the 74H00 E90 so the K5-3 FALSE BR L signal is inactive. At least that part of the hardware looks OK.

• We setup the 'scope to look at the IR Register latches to see if it is actually latching all of the instruction bits correctly. We set the KM11 to stop the microcode on an address match, toggled in a word with just a single bit set, set the starting address, set the console switches to 000005, and pressed START with ENABLE on. The microcode stopped at step 5 with the current instruction latched in the IR Register. We looked at both the 0 and 1 outputs for E96, E71, E41. and E21. All of the 74175 latches contained the right data, which also means that the Unibus receiver and the D MUX chips are OK.

1/7/26

• We put a SWAB R0 instruction, 000300, at location 001000, did a LOAD ADDR, set the MSTOP switch on the KM11 on, and set the console switches to 000005. When the mirocode stopped it was at address 005/122. This showed that the SWAB instruction was not decoded correctly. We looked at the K3-5 SWAB L signal on pin 2 of the 74H04 E45. It was inactive high even after the microcode stopped. The input signal to E45 ion pin 1 K3-5 SWAB H was always inactive low. 

• We looked at the input and output pins on the 74H11 E51. The output is K3-5 SWAB H and was inactive low. The inputs were pin-9 K3-3 IR6 (1) H inactive low, pin-10 K3-5 IR (15:08)=0 H was active high, and pin-11 K3-3 IR7 (1) H inactive low. All of the inputs should have been active high.

• We looked at the signals K3-3 IR6 (1) H on the 74175 E71 pin-15, and K3-3 IR7 (1) H on the 74175 E71 pin-10. If the input is a 1 we see two K4-2 CLK IR H signals about 1uS apart. The first CLK latches the correct data from the DMUX into the IR Register, and the second CLK causes incorrect data to be latched into the IR. We only see this double CLK if bits 6 & 7 are both on.

• We single-stepped through the microcode starting at the 026/046 console loop to see where the first and second K4-2 CLK IR H signals are generated.

  • Microcode step 004/005 generated just one K4-2 CLK IR H pulse and latched the correct instruction data. The next microcode step was 005/136 which should have been 134. So we are back to the BUT (INSTR 1) BUT 37 not working correctly.

  • The double K4-2 CLK IR H signal is from the BUT (INSTR 1) going to the wrong microcode address. The first K4-2 CLK IR H signal is generated at 004/005, and the second after it branches to 136 instead of 134.

• We are back to looking at the K3-5 BUBC1(BUT37) H signal to see why it is high when it should not be.

  • We set the 'scope up to look at the STB signals for the 74150 chips that latch the selected input signals. The STB signal for K3-2 BUBC0(BUT37:20) L and K3-2 BUBC1 L is different from BUBC2 L and BUBC3 L, and again from BUBC4 L and BUBC5 L. These STB signal are all derived from the UBF signals. In the case of BUT37 they should all be active.

  • We single-stepped the microcode after pressing START and then CONT. When the microcode got to 004/005 is strobed the BUT MUX latches. The bit-0 output on E81 pin-10 was inactive high, which is OK. The output on E72 pin 10 was active low, which is wrong. Signal K3-5 BUBC1 (BUT37) H was high, which is wrong.

  • We looked at the inputs to the 74H52 E53 that makes the K3-5 BUBC1 (BUT37) H signal. Pins 1, 2, 12, and 13 were all high which would make the output incorrectly high. These pins are driven by the K3-5 I1K1 H signal. These are the only combination of signals that would make the output of E53 high.

  • The K3-5 I1K1 H signal comes from the 74H30 E68. If any if the inputs are low the output will be high. The input pin-1, K3-6 PARTDOP*RE0 L, is low which will cause the output to be incorrectly high. E70 pin 5, K3-6 SWAB*DM0 is low, which is correct for a SWAB instruction.

  • The K3-6 PARTDOP*RE0 L comes from pin-6 of the 74H50 E49. Input pins 4 & 5 are high which would make the output incorrectly go low. Pin-4 comes from the 74H04 E37 that is the inverted signal K3-3 DM0=0 L. The signal K3-3 DM0=0 L is active low. The signal on pin-5 of E49 comes from the 74H21 E38 on sheet K3-6. All of the inputs to E38 need to be high to make the output high. Pins 9, 10, and 13 are all being driven high, Pin 12 is only driven to 1.8V so we found a problem with the signal K3-3 IR (14:12)=0 L.

  • The K3-3 IR (14:12)=0 L signal comes from the 8251 E11 pin-13. E11 pin-13 is a solid logic low level. Could this be a problem with a high resistance PC trace between E11 pin-13, and E38 pin 12?

  • We looked at what signals go to the 74H20 E66 that we already replaced on this IR Decode board. We didn't find the K3-3 IR (14:12)=0 L signal so our workmanship didn't break the K3-3 IR (14:12)=0 L signal trace.

1/10/26

• • We looked on the schematic for other chips that have the K3-3 IR (14:12)=0 L signal as an input so we can follow the PC trace and maybe find the disconnect. It goes from K3-3 8251 E11 pin 13, to  K3-5 8815 E22 pin 12, to K3-5 8815 E23 pin 4, to K3-5 E33-15, to K3-6 74H21 E38 pin 12, and to K3-5 74H00 E43 pin 9. The break in the PC trace was under E38. We used blue Wire-Wrap wire from a DEC field service kit to jumper from the PC trace to pin-12 on the IC. We now have continuity from the source to all destination ICs.

  • We toggled in a few SWAB instructions and put 000377 in R0. After executing the SWAB instruction R0 contained 177400, so the SWAB instruction is now working. 

  • Cully brought his Unibone. He installed it in the I/O backplane and we will try to get it to emulate a disk drive. It misbehaved, so back to debugging.

  • We loaded PDP-11 BASIC from a paper tape image, and it actually ran.

  • We booted XXDP and RT-11 from RL02 images from the Unibone.

  • We used PDP-11 GUI to load BQEAC1.BIC, the KD11-A CPU Diagnostic. We let it run for about 42 passes, so the core of the processor is probably OK.

  • We ran CMFAF1.BIC from XXDP, 11/35/40/45 MS11,MF11,MA11-P PARITY TEST.  It is failing a program address 007070. Earlier we added jumpers to disable MF11-LP Core Memory because it is not installed. That probably disabled memory parity error traps, so the diagnostic fails.

  • Cully, Dan-2, and Cully's friend from Virginia removed the RX02 from the rack, disassembled it, and removed the rest of the mouse nest from the left drive. After cleaning the mouse poop from the lead screw and lubricating it, the head moved easily. We reassembled the RX02, put it back in the cabinet, and wired it to the RX211 controller. When we press START with the switch in the HALT position both RX02 heads recalibrate to to track zero, but only the right head solenoid clunks.

  • We discussed whether we should install and debug the EIS, FIS, MMU, Line Clock, and Stack Limit boards, or if we should install two RL02 drives and the controller. My vote is to install and debug processor options one-at-a-time, and use my Unibone for the disks until the processor is completely debugged.

1/14/26

• We installed the KD11-E EIS and KD11-F FIS boards, and removed jumper W1 on the IR Decode board.

• After power on we were able to run ODT from address 765020 on the M3212 Bootstrap Terminator board.

• We tried to boot RT11 from an RX02 diskette, but all we observed was rapid repeating head recalibrations.

• We used PDP-11 GUI to load Maindec-11-DCKBA-A-D SXT Instruction Test.

  • • We let it run for several minutes without errors.

• We used PDP-11 GUI to load BQEAC1.BIC, the KD11-A CPU Diagnostic.

  • • We let it run for 30 passes without errors, so adding the KE11-E EIS and KE11-F FIS boards didn't break the processor.

  • There is a series of diagnostics to run to test the individual instructions that the KE11-E EIS board provides.

  • We used PDP-11 GUI to load Maindec-11-DCKBI-A-D ASH Instruction Test

    • We let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBJ-A-D ASHC Instruction Test

    • We let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBK-A-D MUL Instruction Test

    • We let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBL-A-D DIV Instruction Test

    • We let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCQKA-A-D MUL/DIV Exerciser

    • We let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DBKEA-A-D FIS Instruction Test

    • We let it run for 10 minutes without errors.

  • We tried to use PDP-11 GUI to load Maindec-11-DBKEB-A-D FIS Instruction Exerciser. The diag in memory doesn't match the source listing. Maybe the binary file is bad?

1/17/26

• We used PDP-11 GUI to load the version of the Maindec-11-DBKEB-A-D FIS Instruction Test paper tape image that "Hunta" provided. It is also missing the JMP instructions at address 000200. We tried starting it at the BEGIN address of 001010, but it immediately halted. Looking at the PDP-11 GUI Memory Loader window, the diag file contents don't match the source code listing. We will have to use XXDP to run the program.

• We installed Mike's Unibone and Dan figured out how to get it to emulate an RL02 with the XXDP V2.5 pack mounted. We loaded Maindec-11-DBKEB-A-D FIS Instruction Exerciser from XXDP and let it run for about 15 minutes. No errors were reported.

• We were able to boot RT-11 from Cully's Unibone, but not from Mike's. Looks like we have some debugging to do.

• We ran the CZM9BE0 M9312/1144 UBI Bootstrap diag. It said that we have the following boot ROMs on the board, but complained about the boot order. It wants the DL ROM first. We need to find or make a 23-756A9 ROM for DECtape and a 23-761A9 ROM for DECassette. There are only four ROM locations so we will remove the 23-760A9 Paper Tape Reader ROM.

  • • BOOTSTRAP ROM ENTRY POINTS AND DEVICE CODES

    • LOC.             NO DIAG.       RUN DIAG.       DEVICE CODE

    • ROM 1(E35)      173004          173006          DY

    • ROM 2(E33)      173204          173206          PR

    •                 173234          173236          TT

    • ROM 3(E34)      173404          173406          DL

• We successfully ran CQKCG1.BIC 1140/1145 Instruction Exerciser from XXDP for more than an hour. Looks like the processor is OK.

• We installed the KW11-L  Line Time Clock board and ran the Maindec-11-DZKWA-A-D KW11-L Line Frequency Clock diag for 10 passes.

1/21/26

• Take pictures of the EIS and FIS boards so we can determine what revision level they are. There is a giant ECO for the EIS board.

• Move jumper W1 on the Timing Board, move jumper W1 on the Status Board,

• Install the KJ11-A Stack Limit board, and run diags.

• Remove jumpers W1, W3, W4, W5, W6, W7, W8 and W9, and move jumper W2 and W10 on the Data Paths Board, install C114 & C115 on the Timing Board.

• Install the KT11-D Memory Management Option and run diags.

• See if it will boot XXDP or RT11 from an RX02 diskette. We likely have issues with either the Diskette controller or the Diskette drives, so we will need to do some debugging.

PDP-11/40 Diagnostics

KD11-A PDP-11/40 Processor
BKDMD0.BIC 1140/1135 T14 Traps Test
BKMAA0.BIN 1140/1135 Basic Memory Timing

BQAAA0.BIC 1140/1135 Watchdog Timer

BQEAC1.BIC 1140/1135 KD11-A CPU Diagnostic 14-Jan-26
CQKCG1.BIC 1140/1145/1160/1165 Instruction Exerciser 17-Jan-26

ZKAQH0.BIC PDP11 Power Fail

KT11-D Memory Management

BKTAD0.BIC 1140/1135 KT11-D Logic

BKTBB0.BIC 1140/1135 KT11-D Keys

BKTCB0.BIC 1140/1135 KT11-D Moves

BKTDC0.BIC 1140/1135 KT11-D States

BKTFD0.BIC 1140/1135 KT11-D Abort

BKTGD1.BIC 1140/1135 KT11-D Exerciser

KW11-E EIS

Maindec-11-DCKBI-A-D ASH Instruction Test 14-Jan-26

Maindec-11-DCKBJ-A-D ASHC Instruction Test 14-Jan-26

Maindec-11-DCKBK-A-D MUL Instruction Test 14-Jan-26

Maindec-11-DCKBL-A-D DIV Instruction Test 14-Jan-26

Maindec-11-DCQKA-A-D MUL/DIV Exerciser 14-Jan-26

Maindec-11-ZKEBB0 1135/1140 KE11 EAE Basic Logic Test
Maindec-11-ZKECA0 1135/1140 EAE Random Exerciser

KW11-F FIS

Maindec-11-DBKEA-A-D FIS Instruction Test 14-Jan-26

Maindec-11-DBKEB-A-D FIS Instruction Exerciser 17-Jan-26

Maindec-11-DBKE0-A-D GTP Overlay

KW11-L Line Time Clock

Maindec-11-DZKWA-A-D KW11-L Line Frequency Clock 17-Jan-26

KJ11-A  Stack Limit Option
Maindec-11-DCKBF-B KJ11-A Stack Limit Test

DZ11 8 Line Asynchronous Multiplexer

Maindec-11-CZDZAG0 DZ11 Asynchronous Multiplexer Test

LK11 Bush Button Box

Maindec-11-DZLKA-A LK11A Push Button Module Diagnostic

MS11-LD 128kW MOS Parity Memory

Maindec-11-ZMSDD0.BIN MS11L/MS11M Memory Test
Maindec-11-ZMSPC0.BIN MS11L/MS11M/MS11P Memory Test
Maindec-11-ZQMBG2.BIN 0-124K Memory Exerciser 8K

Maindec-11-ZQMCH0.BIC 0-124K Memory Exerciser 16K

M9312 Boot/Terminator

Maindec-11-ZM9BE0.BIC M9312/1144 Boot Terminator 17-Jan-26

DEUNA/DELUA Ethernet

Maindec-11-ZUACD0.BIC DEUNA Exerciser

Maindec-11-ZUADB1.BIC DELUA Exerciser

RL11/RL02 Disk Controller and Drive

ZRLGE0.BIC RL11/RLV11 Controller #1
ZRLHB1.BIC RL11/RLV11 Controller #2
ZRLID1.BIC RL01/RL02 Drive Test #1
ZRL1C0.BIC RL01/RL02 Drive Test #2
ZRLKB3.BIC RL01/RL02 Performance Exerciser
ZRLLC1.BIN RL01/RL02 Drive Compatibility
ZRLMC0.BIN RL01/RL02 Bad Sector File Test
ZRLNC0.BIN RL01/RL02 Drive Test #3

RX211/RX02 Diskette Controller and Drive

ZRXAF0.BIC RX11 System Reliability Test
ZRXBF0.BIC RX11 Interface Diagnostic
ZRXCA0.BIN RX02 Performance Exerciser
ZRXDC0.BIC RX02 Subsystem Verify
ZRXEA2.BIC RX02 Formatter
ZRXFB0.BIC RX02 Functional Controller

TA11/TU60 DECassette  Controller and Drives
ZTAAC0.BIN TA11 Logic Test #1

ZTABC0.BIN TA11 Logic Test #2

ZTACC0.BIN TA11 Manual Intervention

ZTADD0.BIN TA11 Motion Test

ZTAEC0.BIC TA11 Data Reliability

ZTAFC0.BIN TA11 Cassette Loader

ZTAHA0.BIN TA11 Cassette Duplicator

TC11/TU56 DECtape Controller and Drive

ZTCAA0.BIC TU56/TC11 TC1 Basic Logic

ZTCBE0.BIC TU56/TC11 TC2 Basic Logic

ZTCCA0.BIC TU56/TC11 TC3 Basic Logic

ZTCDC0.BIC TU56/TC11 TC4 Basic Logic

ZTCED0.BIC TU56/TC11 TC5 Basic Logic
YPTCB0.BIN TC11 DecTape Formatter

VT11 Graphics

DGTAD2.BIN GT40 Instruction Test 1

DGTBD0.BIN GT40 Instruction Test 2

DGTCC0.BIC GT40 Visual Test

DGTDD0.BIN GT40 Rom Verify

DGTED0.BIN GT40 Quick Verify

DGTGB0.BIC GT40/GT44 Visual Display Test

Ultrix-11 Notes:

Set the terminal to 9600, E71

Use lower case to login or else it will always use upper case

Default Maintenance Userid/Password is; field/service
To shutdown Ultrix: From the root user, /etc/shutdown -h now
To boot Ultrix: @dl

Programmer's Console Cable Connections

Repairs:

• 11/24/25 Replaced the SN74153 E38 on the M7231 Data Paths board to fix a stuck bit-10 data problem.

• 12/31/25 Replaced the SN74H20 E66 on the M7233 IR Decode board to fix the HALT instruction.

• 1/10/26 Fix a broken trace for the K3-3 IR (14:12)=0 L signal under E38 on the M7233 IR Decode board to fix the SWAB instruction.

To Do:

• Install jumper W5 on the M7234 Timing board because we don't have core memory. (Done 28-Dec-25)

• Replace the modified filler panel below the front console with a normal filler panel. (Done 29-Oct-25)

• Replace the damaged KY11-D Programmer's Console with an undamaged one. The old and new chassis have different Programmer's Consoles and mounting brackets. The power enable wires connect to the left side on the old design and to the right on the new design. (Done 29-Oct-25)

• Remove the non-DEC power supplies that are mounted to the rear swing frame. (Done 29-Oct-25)

• Remove the PDP-11/23 boards and Q-Bus backplane from the CPU cabinet. (Done 29-Oct-25)

• Remove the Tektronix RM504 oscilloscope and lab power supply from the CPU cabinet. The idea was to install this oscilloscope in the PDP-9 as a future graphics display, but we really should use an RM503. We have several RM503 oscilloscopes in the warehouse to choose from. (Done 29-Oct-25)

• It might be a good idea to use one of the newer design CPU chassis. The newer chassis design, S/N 5000 and up, has an improved power distribution system. We have the three of newer chassis. One is in an empty cabinet, and two empty ones in the PDP-11/45 expansion cabinets. If the newer chassis is an expansion chassis, it might not have the signals for the line clock wired to the CPU backplane, or the wires that go from the Programmer's Console key switch to the AC Power Controller.

• If we use the older design chassis: (1-Nov-25 we decided to use the newer design chassis)

  • Repair or replace the first power distribution backplane.

  • Repair the first power supply to power distribution backplane connector on the power harness.

• Repair the AC power wiring for the fans in the power supply. (Done 19-Nov-25)

• Connect the terminals on the PDP-11/40 console to the remote input connector on the 861C AC Power Controller in the bottom of the cabinet. (Done 6-Dec-25)

• Test and possibly repair the AC and DC power subsystems. (Done 12-Nov-25)

• Test and possibly repair the upper and lower fans in the CPU chassis and in the power supply. Upper fan is repaired, the rear lower fan is seized.

• Install the PDP-11/40 CPU backplane and CPU boards in the CPU chassis. Leave the KD11-E EIS Option, KD11-F FIS Option, KT11-D Memory Management Option, KJ11-A Stack Limit, and Kw11-L Line Time Clock boards out of the CPU backplane for the initial testing. Note: There are a bunch of jumpers that need to be changed if these options are left out. (Done 12-Nov-25)

• Install the M9312 Bootstrap/Terminator in slot 9AB of the CPU backplane. (Done 12-Nov-25)

• Test and possibly repair the KY11-D Programmer's Console. (Done 12-Nov-25)

• Test and possibly repair the KD11-A CPU. Note: The 11/35 has another CPU board set, and Mike has another CPU board set at home. (Done 10-Jan-26)

• Test and possibly repair the DL11 Asynchronous Line Interface Board. (Done 10-Jan-26)

• Install the I/O expansion backplane in the CPU chassis. Move the M9312 to slot 16AB in the expansion backplane and install a M981 Unibus Jumper from slot 9AB to 10AB. (Done 19-Nov-25)

• Perform simple tests on the MS11-LD 128kW MOS Memory board and possibly repair it. (Tested 10-Jan-26) Needs debugging.

• Connect a laptop to the DL11, load PDP-11 GUI and verify that the CPU, Memory, and I/O board diagnostics run OK.  (Done 10-Jan-26)

• Verify that the minimal CPU board set, the MS11-LD 128kW MOS Memory, and any of the I/O boards that are in the expansion backplane pass diagnostics.  (Done 10-Jan-26)

• Install the KD11-E EIS CPU Option in the CPU backplane and verify that it passes diagnostics. (Done 14-Jan-26)

• Install the KD11-F FIS CPU Option in the CPU backplane and verify that it passes diagnostics. (Done 14-Jan-26)

• Install the KT11-D Memory Management Option in the CPU backplane and verify that it passes diagnostics.

• Install the KJ11-A Stack Limit Option in the CPU backplane and verify that it passes diagnostics.

• Install the TU60 in the top of the CPU cabinet. Install the TA11 controller in the I/O backplane and connect it to the TU60.

• Test and possibly repair the TA11 and TU60. There is lots of restoration info here.

• Install the RX02 diskette drive in the I/O cabinet. (Done 11/30/25)

• Connect the RX02 to the RX211 board. (Done 10-Jan-26)

• Create RX02 XXDP media using PDP-11 GUI and see if we can boot the XXDP Diagnostic Monitor from diskette. Note: The M9213 Bootstrap/Terminator board has the DY (RX02) boot ROM.

• Install the TU56-H DECtape drive in the I/O cabinet with the TC11 DECtape controller. (Done 11/30/25)

• Connect the TC11 to the end of the Unibus in the 11/40 chassis. Move the Unibus terminator from the CPU chassis to the TC11 chassis.

• Test and repair the TC11 and the TU56-H.

• Install two RL02 drives in the DECtape cabinet.

• Install scratch media in the RL02 drives and run the disk drive diagnostics.

• Install XXDP or RT-11 media in one of the RL02 drives and see if the Diagnostic Monitor or Operating System will boot.

• Install the VT11 backplane and boards in the CPU chassis. Move the M9312 to slot 17BC in the expansion backplane and install a M981 Unibus Jumper from slot 16AB to 17AB.

• Install the VR14 in the CPU cabinet and leaving a 3U gap above the CPU chassis. (Done 29-Nov-25)

• Connect the VR14 to the VT11 and see if the diagnostics will run.

• Create BSD2.9 UNIX RL02 media and see if it will boot.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.

• Connect the two RL02 disk drives to the RL11 controller.

• Replace the DL11 with a DZ11, connect it to the RS-232 distribution panel, and see if the diagnostics will run.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.

HALT Instruction Debugging Notes:

• • The K2-8 CLKIR (1) H signal comes from the Microcode board and enables the clock pulses on print K4-2.

  • The K2-8 CLK0FF (1) H signal comes from the Microcode board and is how the microcode turns off the processor clock. When this signal is active the Clock IDLE flip-flop (K4-2) will turn on and the Clock RUN flip-flop will turn off.

  • On page 1 of the microcode Flow Diagram, step 004 (FET04) will use BUT(INSTR 1) (BUT 37) to determine the future address. Step 005 (FET05) restores the R[PC], and then should branch to step 122 (CON00) on page 11. On page 11 we see the microcode enter the normal console code where it waits for a console button press. A CONT button press would restart the program running.

  • The IR Decode board schematic page K3-8 shows the source of the K3-8 HALT+RESET L signal.

  • The IR Decode board schematic page K3-5 shows the source of the K3-5 BUBC* (BUT37) H signals. There is a lot of random logic used to generate these signals which will take a lot of debugging if it is broken.

  • The 9-bit UPP Register on the K2 Microcode Board determines which microword will be selected in the ROMs. The address is the NOR of the BUS U [08:00], the BUBC [5:0], and the EUBC [8:1].

  • The 74174 E5 latch that makes PUPP(3:0) register on the Microword board is on sheet K2-2. The outputs should be displayed on the KM11 lights. The lights will likely display 123 or 133 when they should show 122. We can trigger the 'scope when CLK goes high and look at the inputs and outputs for K2-2 PUPP0 (1)H and K2-2 PUPP3 (1)H. Both should be low for the 122 microword address. Since the problem has been proven to be on the IR Decode board we can assume that the 

  • Microword 004 (FET04) has UBF = 037 to use BUT (INSTR 1) (BUT 37) to determine the offset to the base microcode address. At microcode address 005 the U WORD ROMS on K2 > BUS U [08:00] contains the base address of 100 in the UPF bits. The offset is from the IR REG in K3 > U BRANCH CONTROL on K3 > BUBC [5:0] (BUT XX) > BUT MUX on K3-2. The offset should be 22 but is 23 or sometimes 33 resulting in a jump to microword 123 or 133 instead of 122.

  • We need to stop the microcode at word 005 and look at the state of the BUS U [08:00] from the U Word board and the BUBC [5:0] signals from the IR Decode board. Since the IR Decode board causes the HALT problem the BUS U [08:00] signals are probably OK and the problem is really on the BUBC [5:0] signals. The input and output of the BUT MUX might be the place to look first. If the output of the BUT MUX is OK then the NOR gate to the UPP register might be broken.

  • The BUT MUX is on schematic sheet K3-2. Signal K3-2 BUBC0 (BUT37:20) L comes from the 74150 E81 on the IR Decode board. The MUX should have S0..S3 all high to select the BUBC5..0 (BUT37) H signals, and STB low to enable the chip. The K2-5 UBF4 (1) L will enable E72 and E81 to make the K3-2 BUBC0 (BUT37:20) L and K3-2 BUBC1 L signals. The 74151 E90 supplies the K3-2 BUBC3 L signal. We need to check that signal too. The K3-5 BUBC5..0 (BUT37) bits for the HALT instruction should be 010010 and are on schematic sheet K3-5. We should check the 74150 E97 to insure that the STB input is high and the f output is high.

  • The K3-5 BUBC5..0 signals go to the BUT MUX and then to the NOR gates on K2-2.

Memory Parity Traps:

• The MS11-LD memory board manual says that if bit-0 in the CSR at address 772100 is set to a 1 the memory board will drive the Unibus signal BUS PB L if there was a parity error. We should only see a parity error when we EXAM uninitialized memory, not when we DEP memory.

• Determine if the MS11-LD memory board is driving the Unibus signal BUS PB L low when we DEP to uninitialized memory. If not, then investigate why the processor microcode is branching to the TRAP ERR microcode on the microcode flow chart sheet 6 when we DEP.

Trap Debugging Notes:

• A memory parity error will set the PERR flip-flop on schematic sheet K4-3 for the Timing board. We should look at the state of the PERR flip-flop E24 on pin 8 to see if the flip-flop gets set when we DEP. If so we can work our way back through the logic to the BUS PB L signal on pin 5 of the 380 chip E1. If the Unibus signal BUS PB L is being driven low when we DEP we need to investigate the MS11-LD memory board, or disable the memory error Trap.

• Removing jumper W8 on the Status board, schematic sheet K5-5, enables the memory parity error trap. For now we should make sure that W8 is installed.

• The MS11-LD the CSR address is 772100. The MS11-L technical manual says that the parity error logic is enabled during a memory read cycle. We have not found the read enable circuitry yet. When bit-0 in the CSR is a 1 the memory board will drive the Unibus signal BUS PB L if there was a parity error. If bit-15 is of the CSR on and the red LED is on there has been a parity error. It looks like the parity checking logic will detect a parity error when writing, but should not do anything. The CSR00 H signal from bit-0 of the CSR on pin 7 of E15 (sheet 8) should be low and at pin-2 of E16 (sheet 7) and the output signal PAR ERR EN L will be high so BUS PB L (pin-AN2 on the backplane) from pin-15 E1 (sheet 2) will not be driven. Eventually we should be able to run MAINDEC-11-CZMQC to test the memory board.

SWAB Debugging Notes:

• We need to test the IR Decoders E80, E61, E31, and E11 on the IR Decoder board K3-3. The SWAB instruction format is 0003dd where dd is the register number. We have been using the instruction 000300 for SWAB R0 in our testing. This instruction should turn on signal K3-3 DM=0 L from pin 13 of the 8251 Decoder E80, K3-3 IR (08:06)=3 L from pin 10 of E61, K3-3 SM=0 L  from pin 13 of E31, and K3-3 IR (14:12)=0 L from pin 13 of E11.

• At microword 004 we have the branch (INSTR 1) or BUT(37). This adds an offset to the base address of 100 to branch to the individual instruction microcode. In this case the offset is 22 instead of 34 so the microcode is branching to address 122 HALT instead of 134 SWAB instruction.

• On sheet K3-2 of the IR Decode, microword 004 has UBF=37 to use the BUT 37 MUX inputs to determine the offset for branching. Having UBF (4:0) bits on will select the D15 input of the 74150 MUX chips. Signal K3-2 BUBC1 L is active and should not be. Signal K3-2 BUBC2 L is inactive and should be. Signal K3-2 BUBC3 L is inactive and should be.

• On the input of 74150 MUX E71, K3-5 BUBC1 (BUT37) H is active and should not be, 74151 MUX E98, K3-5 BUBC2 (BUT37) H is inactive and should be, and 74151 MUX E90, K3-5 BUBC3 (BUT37) H is inactive and should be.

• It might be easiest to look at the inputs on the 74H52 AND/OR gate E53 to determine what signals are active that should not be. Since the IR Register seems to be working correctly and contains 0000300 the input signals K3-3 IR10 (1)H and K3-3 IR04 (1)H should be inactive. That only leaves signal K3-5 I1K1 H on E53 pins 01, 02, 12, and 13 as the trouble maker. That signal comes from the 74H30 8 input NOR gate E68. We will need to look at all of the inputs to see which one is low and causing trouble.

• We should look at the K3-6 SWAB*DM0 L signal from the 74H00 NAND gate E58. That is the NAND of K3-5 SWAB H and K3-3 DM=0 L inverted. There is also a K3-5 SWAB L we should look at to make sure the 74H04 inverter E45 is working.