PDP-11/40 #2
Restoration 2026

Back to the 2025 restoration blog.

1/3/26

• If we DEP and EXAM a register everything works OK. If we EXAM memory it works OK, but if we DEP memory the processor goes into space. We stepped through the DEP microcode starting at 034. When the microcode gets to step 072/030 it is doing the Unibus write. Instead of branching to step 030 it actually went to 336/317. Ashlin pointed out that these are the addresses of the TRAP ERR microcode.  The current thought is that when the Unibus write happened the memory board drove BUS PB L signal to report a memory parity error. It should never report a parity error on a memory write.

• Jumper W8 on the Status board disables the Parity Error Trap. It was installed on our Status board. For good measure we resoldered the jumper. Now we can DEP without problems.

• We toggled in Ashlin's counting program from: https://blog.tephra.me/pdp-11-40-test/ The PDP-11/40 is actually running its first program! Ashlin's Light Chaser program also runs.

• We started working on the M7800 DL11 serial port for the console. The crystal in ours is 4.608 MHz, so it will support 9600 baud. 9600 7E1 is probably the preferred console port configuration.

  • 777560 Receiver Status Register

  • 777562 Receiver Buffer Register

  • 777564 Transmitter Status Register

  • 777566 Transmitter Buffer Register

• We toggled in one of Ashlin's programs that sends a stream of As out the serial console. We connected a serial breakout box to the console cable and pin-3 RD data was constantly lit. We connected a VT220 terminal to the breakout box and when we typed on the keyboard pin-2 RD data lit. That means we didn't have a DTR-DSR configuration conflict and don't need a null-modem adapter. The VT22o displayed a stream of "P" characters. The program said that it would send a stream of "A" characters, so we have a problem. We tried other characters, and they worked OK. We went back to the "A" character and it worked.

• The M9312 bootstrap terminator board has a Console Emulator ROM as well as a few Bootstrap ROMs. 

  • The Console Emulator starting address is 165020

• Starting the Console Emulator at the normal address results in the processor halting at 165052. When it halted the Z & C indicators were on and R3 was zeros.

• Pressing CONT resulted in a halt at 165466. 

• The Console Emulator ROM matches this listing

  •       165020 005003               T1: clr r3 ; R3=000000 C=0

  •       165022 005203                  inc r3 ; R3=000001 C=0

  •       165024 005103                  com r3 ; R3=177776 C=1

  •       165026 006203                  asr r3 ; R3=177777 C=0

  •       165030 006303                  asl r3 ; R3=177776 C=1

  •       165032 006003                  ror r3 ; R3=177777 C=0

  •       165034 005703                  tst r3 ; R3=177777 C=0

  •       165036 005403                  neg r3 ; R3=000001 C=1

  •       165040 005303                  dec r3 ; R3=000000 C=1

  •       165042 005603                  sbc r3 ; R3=177777 C=1

  •       165044 006103                  rol r3 ; R3=177777 C=1

  •       165046 005503                  adc r3 ; R3=000000 C=1

  •       165050 000303                  swab r3 ; R3=000000 C=0

  •       165052 001377                  bne . ; br . if FAIL

• We single-steeped through the register test code and found that SWAB instruction causes a HLT. We ran the rest of the Console Emulator ROM and each SWAB instruction caused a HLT. Time to step through the SWAB microcode to see what it does.

• We executed a SWAB instruction (000303) and stopped the microcode with a match at address 016. The microcode address sequence then was 001, 004, 005, 122. It looks like it is interpreting a SWAB as a HALT. Probably another problem in the IR Decode board.

• We looked at the K3-5 BUBC0(BUT37) H, K3-5 BUBC1(BUT37) H, K3-5 BUBC2(BUT37) H, and K3-5 BUBC3(BUT37) H signals on the IR Decode board with the 'scope. We entered a bunch of SWAP R0 instructions and pointed the PC to them. We pressed START, stopped the microcode at 032, and stepped the microcode through START until it got to 004/005. The BUBC0..BUBC3 signals were all high. The next microcode step went to 137.

• We looked at pin 8 of E52 on the IR Decode board. It was high, so that would make the microcode branch to the wrong address. We looked at the inputs and found that pins 1 & 2 were high, so there is a problem. We looked at pin 8 of E66 (the one that we replaced Wednesday), and it was high. We looked at the inputs on E66 and found pin 13 was low. That is signal K5-3 FALSE BR L from the Status board.

1/4/26

• We setup the 'scope to look at E90 on the Status board, the source of the K5-3 FALSE BR L signal. We put a SWAB instruction in memory at 1000, put 1000 in the PC, set the KM11 MSTOP switch on, and set the console switches to stop at microword 005. When we pressed START with the ENABLE switch on, the microcode stopped at address 005, just where it is decoding the instruction. 

• It looks like we have multiple problems. The next microcode address is 113, where it should be 134 for a SWAB instruction. It is now not decoding some instructions correctly. We reentered Ashlin's counting program, and it ran OK. At least the processor is decoding CLR, INC, and BR instructions correctly.

• We also see pin-1 high, pin-2 low, and pin-3 high on the 74H00 E90 so the K5-3 FALSE BR L signal is inactive. At least that part of the hardware looks OK.

• We setup the 'scope to look at the IR Register latches to see if it is actually latching all of the instruction bits correctly. We set the KM11 to stop the microcode on an address match, toggled in a word with just a single bit set, set the starting address, set the console switches to 000005, and pressed START with ENABLE on. The microcode stopped at step 5 with the current instruction latched in the IR Register. We looked at both the 0 and 1 outputs for E96, E71, E41. and E21. All of the 74175 latches contained the right data, which also means that the Unibus receiver and the D MUX chips are OK.

1/7/26

• We put a SWAB R0 instruction, 000300, at location 001000, did a LOAD ADDR, set the MSTOP switch on the KM11 on, and set the console switches to 000005. When the mirocode stopped it was at address 005/122. This showed that the SWAB instruction was not decoded correctly. We looked at the K3-5 SWAB L signal on pin 2 of the 74H04 E45. It was inactive high even after the microcode stopped. The input signal to E45 ion pin 1 K3-5 SWAB H was always inactive low. 

• We looked at the input and output pins on the 74H11 E51. The output is K3-5 SWAB H and was inactive low. The inputs were pin-9 K3-3 IR6 (1) H inactive low, pin-10 K3-5 IR (15:08)=0 H was active high, and pin-11 K3-3 IR7 (1) H inactive low. All of the inputs should have been active high.

• We looked at the signals K3-3 IR6 (1) H on the 74175 E71 pin-15, and K3-3 IR7 (1) H on the 74175 E71 pin-10. If the input is a 1 we see two K4-2 CLK IR H signals about 1uS apart. The first CLK latches the correct data from the DMUX into the IR Register, and the second CLK causes incorrect data to be latched into the IR. We only see this double CLK if bits 6 & 7 are both on.

• We single-stepped through the microcode starting at the 026/046 console loop to see where the first and second K4-2 CLK IR H signals are generated.

  • Microcode step 004/005 generated just one K4-2 CLK IR H pulse and latched the correct instruction data. The next microcode step was 005/136 which should have been 134. So we are back to the BUT (INSTR 1) BUT 37 not working correctly.

  • The double K4-2 CLK IR H signal is from the BUT (INSTR 1) going to the wrong microcode address. The first K4-2 CLK IR H signal is generated at 004/005, and the second after it branches to 136 instead of 134.

• We are back to looking at the K3-5 BUBC1(BUT37) H signal to see why it is high when it should not be.

  • We set the 'scope up to look at the STB signals for the 74150 chips that latch the selected input signals. The STB signal for K3-2 BUBC0(BUT37:20) L and K3-2 BUBC1 L is different from BUBC2 L and BUBC3 L, and again from BUBC4 L and BUBC5 L. These STB signal are all derived from the UBF signals. In the case of BUT37 they should all be active.

  • We single-stepped the microcode after pressing START and then CONT. When the microcode got to 004/005 is strobed the BUT MUX latches. The bit-0 output on E81 pin-10 was inactive high, which is OK. The output on E72 pin 10 was active low, which is wrong. Signal K3-5 BUBC1 (BUT37) H was high, which is wrong.

  • We looked at the inputs to the 74H52 E53 that makes the K3-5 BUBC1 (BUT37) H signal. Pins 1, 2, 12, and 13 were all high which would make the output incorrectly high. These pins are driven by the K3-5 I1K1 H signal. These are the only combination of signals that would make the output of E53 high.

  • The K3-5 I1K1 H signal comes from the 74H30 E68. If any if the inputs are low the output will be high. The input pin-1, K3-6 PARTDOP*RE0 L, is low which will cause the output to be incorrectly high. E70 pin 5, K3-6 SWAB*DM0 is low, which is correct for a SWAB instruction.

  • The K3-6 PARTDOP*RE0 L comes from pin-6 of the 74H50 E49. Input pins 4 & 5 are high which would make the output incorrectly go low. Pin-4 comes from the 74H04 E37 that is the inverted signal K3-3 DM0=0 L. The signal K3-3 DM0=0 L is active low. The signal on pin-5 of E49 comes from the 74H21 E38 on sheet K3-6. All of the inputs to E38 need to be high to make the output high. Pins 9, 10, and 13 are all being driven high, Pin 12 is only driven to 1.8V so we found a problem with the signal K3-3 IR (14:12)=0 L.

  • The K3-3 IR (14:12)=0 L signal comes from the 8251 E11 pin-13. E11 pin-13 is a solid logic low level. Could this be a problem with a high resistance PC trace between E11 pin-13, and E38 pin 12?

  • We looked at what signals go to the 74H20 E66 that we already replaced on this IR Decode board. We didn't find the K3-3 IR (14:12)=0 L signal so our workmanship didn't break the K3-3 IR (14:12)=0 L signal trace.

1/10/26

• • We looked on the schematic for other chips that have the K3-3 IR (14:12)=0 L signal as an input so we can follow the PC trace and maybe find the disconnect. It goes from K3-3 8251 E11 pin 13, to  K3-5 8815 E22 pin 12, to K3-5 8815 E23 pin 4, to K3-5 E33-15, to K3-6 74H21 E38 pin 12, and to K3-5 74H00 E43 pin 9. The break in the PC trace was under E38. We used blue Wire-Wrap wire from a DEC field service kit to jumper from the PC trace to pin-12 on the IC. We now have continuity from the source to all destination ICs.

  • We toggled in a few SWAB instructions and put 000377 in R0. After executing the SWAB instruction R0 contained 177400, so the SWAB instruction is now working. 

  • Cully brought his Unibone. He installed it in the I/O backplane and we will try to get it to emulate a disk drive. It misbehaved, so back to debugging.

  • We loaded PDP-11 BASIC from a paper tape image, and it actually ran.

  • We booted XXDP and RT-11 from RL02 images from the Unibone.

  • We used PDP-11 GUI to load BQEAC1.BIC, the KD11-A CPU Diagnostic. We let it run for about 42 passes, so the core of the processor is probably OK.

  • We ran CMFAF1.BIC from XXDP, 11/35/40/45 MS11,MF11,MA11-P PARITY TEST.  It is failing a program address 007070. Earlier we added jumpers to disable MF11-LP Core Memory because it is not installed. That probably disabled memory parity error traps, so the diagnostic fails.

  • Cully, Dan-2, and Cully's friend from Virginia removed the RX02 from the rack, disassembled it, and removed the rest of the mouse nest from the left drive. After cleaning the mouse poop from the lead screw and lubricating it, the head moved easily. We reassembled the RX02, put it back in the cabinet, and wired it to the RX211 controller. When we press START with the switch in the HALT position both RX02 heads recalibrate to to track zero, but only the right head solenoid clunks.

  • We discussed whether we should install and debug the EIS, FIS, MMU, Line Clock, and Stack Limit boards, or if we should install two RL02 drives and the controller. My vote is to install and debug processor options one-at-a-time, and use my Unibone for the disks until the processor is completely debugged.

1/14/26

• We installed the KD11-E EIS and KD11-F FIS boards, and removed jumper W1 on the IR Decode board.

• After power on we were able to run ODT from address 765020 on the M3212 Bootstrap Terminator board.

• We tried to boot RT11 from an RX02 diskette, but all we observed was rapid repeating head recalibrations.

• We used PDP-11 GUI to load Maindec-11-DCKBA-A-D SXT Instruction Test.

  • • We let it run for several minutes without errors.

• We used PDP-11 GUI to load BQEAC1.BIC, the KD11-A CPU Diagnostic.

  • • We let it run for 30 passes without errors, so adding the KE11-E EIS and KE11-F FIS boards didn't break the processor.

  • There is a series of diagnostics to run to test the individual instructions that the KE11-E EIS board provides.

  • We used PDP-11 GUI to load Maindec-11-DCKBI-A-D ASH Instruction Test and let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBJ-A-D ASHC Instruction Test and let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBK-A-D MUL Instruction Test and let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCKBL-A-D DIV Instruction Test and let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DCQKA-A-D MUL/DIV Exerciser and let it run for 10 minutes without errors.

  • We used PDP-11 GUI to load Maindec-11-DBKEA-A-D FIS Instruction Test and let it run for 10 minutes without errors.

  • We tried to use PDP-11 GUI to load Maindec-11-DBKEB-A-D FIS Instruction Exerciser. The diag in memory doesn't match the source listing. Maybe the binary file is bad or it needs the XXDP OS for support?

1/17/26

• We used PDP-11 GUI to load the version of the Maindec-11-DBKEB-A-D FIS Instruction Test paper tape image that "Hunta" provided. It is also missing the JMP instructions at address 000200. We tried starting it at the BEGIN address of 001010, but it immediately halted. Looking at the PDP-11 GUI Memory Loader window, the diag file contents don't match the source code listing. We will have to use XXDP to run the program.

• We installed Mike's Unibone and Dan figured out how to get it to emulate an RL02 with the XXDP V2.5 pack mounted. We loaded Maindec-11-DBKEB-A-D FIS Instruction Exerciser from XXDP and let it run for about 15 minutes. No errors were reported.

• We were able to boot RT-11 from Cully's Unibone, but not from Mike's. Looks like we have some debugging to do.

• We ran the CZM9BE0 M9312/1144 UBI Bootstrap diag. It said that we have the following boot ROMs on the board, but complained about the boot order. It wants the DL ROM first. We need to find or make a 23-756A9 ROM for DECtape and a 23-761A9 ROM for DECassette. There are only four ROM locations so we will remove the 23-760A9 Paper Tape Reader ROM.

  • • .R ZM9BE0

    • ZM9BE0.BIC

    • CZM9BE0 M9312/1144 UBI BOOT

    • DIAG. ROM (E20) (FOR 11-44 UBI: E58)A0

    • BOOTSTRAP ROM ENTRY POINTS AND DEVICE CODES

    • LOC.             NO DIAG.       RUN DIAG.       DEVICE CODE

    • ROM 1(E35)      173004          173006          DY

    • ROM 2(E33)      173204          173206          PR
                                  173234          173236          TT

    • ROM 3(E34)      173404          173406          DL

    • COULD NOT DETERMINE POWER-FAIL VECTOR ADDRESS

    • ROM SEQUENCE IS INCORRECT AS PER INSTALLATION PROCEDURE.

    • SEQUENCE SHOULD BE:

    • ROM 1(E35)      DL

    • ROM 2(E33)      DY

    • ROM 3(E34)      PR

• We successfully ran CQKCG1.BIC 1140/1145 Instruction Exerciser from XXDP for more than an hour. Looks like the processor is OK.

• We installed the KW11-L  Line Time Clock board and ran the Maindec-11-DZKWA-A-D KW11-L Line Frequency Clock diag for 10 passes.

1/21/26

• We ran Maindec-11-ZQMCH0 0-124K Memory Exerciser 16K from XXDP. It immediately complained that we had parity memory, but the parity traps were disabled, so it will not run.

• We moved jumper W2 on the Data Paths board, W1 on the Timing Board, and jumper W1 on the Status Board, and then installed the KJ11-A Stack Limit board.

• We can EXAM memory, but it hangs the processor if we DEP memory. The ODT ROM will not run.

• There just one register on the SLR board at 777774.  At power on it contains 120000. Maybe this should contain 000000?

• The microcode is going into the Trap handler when we press the DEP switch. We removed the SLR board and it still goes into the Trap handler. Maybe changing one of the jumpers enabled some broken logic on one of the boards?

• The microcode for the DEP switch goes through all of the DEP steps, gets to CONSOLE RECYCLE at step 030, and jumps to step 336/317. This is the TRAP ERR handler for (JAMUPP)(RED ZONE+DUBBERR).  It then goes to 215, 115, 326, 327, 113, and loops through 317, 215, 115, 326, 327, 113 over and over.

1/24/26

• • We are still debugging why the Stack Limit Register contains 120000 after an INIT instead of 000000, and why it causes Traps. We only had a dual-wide double-sided extender board so we put both the SLR and Clock boards on the extender board. We used a logic probe for a quick test to verify that the outputs of the 74175 flip-flop E07 were all zeros. We did an EXAM of the SLR register at 777774 and were surprised to see that all of the bits were zeros. We cleaned the dirty gold fingers on the SLR board with DeOxit, and it seems to be working now and not causing Traps. We can EXAM and DEP the SLR OK. So maybe just a case of dirty connector contacts?

  • We started the ODT ROM at 756020 on the M9312 Bootstrap/Terminator board and didn't get a register display on the terminal emulator. We stepped through the ODT code and at address 765124 the address LEDs cleared and data LEDs displayed 000377. It looks like ODT is doing a RAR, SP an causing a trap. We compared the contents of the ODT ROM with a source listing, and we found that bit-7 was always zero. After some more fiddling we found that we cannot read bit-7 from RAM either.

  • After studying the overall schematics we decided that this could be a problem with the B Register, B Mux, ALU, or D register. The input and output of the B Register was OK. We found that the input to the 74153 E60 B MUX was OK, but bit-7 output was always always low. We replaced the 74153 and it didn't fix the problem. After lots of troubleshooting we found that I made a solder bridge from the bit-7 signal to ground when I moved the W2 jumper on the Data Paths board to enable the SRL board. After some quick rework to remove the solder bridge the 11/40 is running ODT and XXDP again.

  • We ran MAINDEC-11-CQKCG2.BIC 1140/1145/1160/1165 Instruction Exerciser from XXDP booted from the Unibone for a few minutes to make sure the processor still ran OK.

1/28/26

• Remove jumpers W1, W2, W3, W4, W5, W6, W7, W8 and W9, and move jumper W10 close to the fingers on the Data Paths Board

• Move jumper W2, Install C113 & C114 on the Timing Board.

• Install the KT11-D Memory Management board.

• The ODT ROM ran, and it booted XXDP from the Unibone.

• It successfully ran:

  • • MAINDEC-11-BKTAD1.BIC 1140/1135 KT11-D Basic Logic Test

    • MAINDEC-11-BKTBB0.BIC 1140/1135 KT11-D Access Keys Test

    • MAINDEC-11-BKTCB0.BIC 1140/1135 KT11-D Moves

    • MAINDEC-11-BKTDC0.BIC 1140/1135 KT11-D Processor States Test

    • MAINDEC-11-BKTFD0.BIC 1140/1135 KT11-D Abort

    • MAINDEC-11-BKTGD1.BIC 1140/1135 KT11-D Exerciser

• That means that everything in the processor is installed and working except for memory parity traps.

• We tried unsuccessfully to boot RT-11 and UNIX V6 from emulated disk drives from the Unibone.

1/3126

• We were not able to boot UNIX V6 from the Unibone. It started to boot and then crashed. It was configured for a PDP-11/34 so it should run on the PDP-11/40. We need to do some homework on this.

• We were able to boot RSX-11M V4.1 from the Unibone. We need to learn how to use RSX11-M before this will be useful. 

• We pulled two RL02 drives and slide rails from the warehouse.  We found that one drive had rust on the spindle, so we will swap that for one in better condition. We installed one RL02 in the I/O rack. We removed the NPR jumper from slot 5, moved the Unibone from slot 7 to slot 5, and installed the RL11 disk controller in slot 7. We cabled the RL11 controller to the RL02 drive, installed a disk pack that was labeled RT11 V5.3, and tried to boot from ODT. It repeatedly reset the Unibus and tried to boot from the pack. We now suspect that all of the RL02 disk packs were wiped before they were donated. We will need to initialize the disk packs and install XXDP and operating systems on the packs.

2/4/26

• We repaired the broken wire in the RL11-RL02 cable.

• We use PDP-11 GUI to look at the RL11 CS (Control & Status) Register @ 774400, BA (Bus Address) Register @ 774402, DA (Disk Address) Register @ 774404, and MP (Multipurpose) Register @ 774406.

• The RL11 registers contained:

  • • CS 140200; ERR (Composite Error), DE (Drive Error) , CRDY (Controller Ready)

    • BA 000000;

    • DA 000000;

    • MP 000234; DT (RL02), HO (Heads Out), BH (Brush Home), Seek

  • We set the CS register to 000004 for a Get Status command, and the DA register to 000013 to Reset and Get the Drive Status.:

  • After the Get Status Command the RL11 registers contained:

    • CS 000204; CRDY (Controller Ready), Get Status

    • BA 000000;

    • DA 000013; Reset and Get the Drive Status

    • MP 000236; DT (RL02), HO (Heads Out), BH (Brush Home), Unload Heads

  • We changed the RL02 disk pack and the drive went ready. When we tried to boot from the drive the READY light flashed repeatedly , and we could hear the RX02 diskette drives recalibrate repeatedly. The RL11 controller Bus Address register contains 000000, so when the boot block is read it should be read into memory starting at address 00000. We examined memory starting at 000000 and it contained all 000000. It lookS like the pack either has been erased, or the boot block was not read.

  • We tried another RL02 disk pack and saw the same results.

  • We installed a scratch RL02 disk pack so we could run diagnostics.

  • We found that the RL02 Drive Select light will go flicker and then go out if the drive is pushed more than half way into the rack. We wiggled cables and everything else and didn't find the problem.

• We use Simh and the XXDP UPDATE command to make an RA80 XXDP disk image and use Win SCP to move it to the Unibone. We made an xxdp.mscp directory and configure the Unibone to boot XXDP, from an emulated RA80 disk. It actually worked!

                               XXDP VERSION 2.2

                             ********************

        ******************** FIELD SERVICE NOTICE ********************

        *                    --------------------                    *

        *  Some diagnostic programs are incompatible with the        *

        *  XXDP V2 Extended Monitor because of their interaction     *

        *  with the Memory Management Hardware. If you are in doubt  *

        *  about the Extended Monitor compatibility of the programs  *

        *  you wish to run, it is reccommended that you boot the     *

        *  Small Monitor.                                            *

        *                                                            *

        **************************************************************

                    S - To boot the Small monitor.

                    X - To boot the Extended monitor.

       Type the letter and then press the RETURN key................. S

           ***********************************************************

           *                                                         *

           *                XXDP V2.2 - SMALL MONITOR                *

           *                                                         *

           ***********************************************************

BOOTING UP XXDP-SM SMALL MONITOR

XXDP-SM SMALL MONITOR - XXDP V2.2

REVISION: C0

BOOTED FROM DU0

28KW OF MEMORY

UNIBUS SYSTEM

RESTART ADDR: 152010

TYPE "H" FOR HELP

.

.R ZRLGE0.BIC

ZRLGE0.BIC

DRSXM-A4

CZRLG-E-0

CZRLG TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION

UNIT IS RL01,RL02

RESTART ADDRESS 141656

DR>STA/PASS:1/FLAGS:HOE

Change HW (L)  ? Y

# UNITS (D)  ? 1

unit 0

RL11=1, RLV11=2, RLV12=3 (O)  ? 1

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

Change SW (L)  ?

No default

Change SW (L)  ? N

• The diag halted at 001274. This doesn't look like a valid halt address.

2/7/26

• We made a new shell script to run the .cmd file to emulate an RA80 disk with an XXDP 2.2 image. We still need to configure the switch script to run this script.

• We connected the ground cable from the RL02 to the cabinet, and installed Mike's RL02 cable. We still have the problem where the READY light flickers and then goes out when you slide in the drive from maximum extension.

• We reran the ZRLGE0 Controller #1, TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION. It ran for a few seconds and halted at 01274, the same as on Wednesday. 

• We swapped the RL11 controller for Mike's known good controller from his 11/84. We reran the ZRLGE0 diag. It ran a pass, didn't halt, and reported problems with the registers.

.R ZRLG??

ZRLGE0.BIC

DRSSM-F0

CZRLG-E-0

CZRLG TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

n

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11=1, RLV11=2, RLV12=3 (O)  ? 1

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

CZRLG DVC FTL ERR  00005 ON UNIT 00 TST 006 SUB 000 PC: 017230

RLBA READ/WRITE ERROR

CONTROLLER: 174400  DRIVE: 0

EXP'D: 000000 REC'D: 100000

CZRLG DVC FTL ERR  00009 ON UNIT 00 TST 010 SUB 000 PC: 017674

BIT SET INSTRUCTION ON RLBA YIELDED WRONG RESULT

CONTROLLER: 174400  DRIVE: 0

EXP'D: 000000 REC'D: 100000

CZRLG DVC FTL ERR  00010 ON UNIT 00 TST 011 SUB 000 PC: 017774

BIT CLEAR INSTRUCTION ON RLBA YIELDED WRONG RESULT

CONTROLLER: 174400  DRIVE: 0

EXP'D: 000000 REC'D: 100000

CZRLG DVC FTL ERR  00014 ON UNIT 00 TST 015 SUB 000 PC: 020366

BUS RESET DID NOT CLEAR RLBA

CONTROLLER: 174400  DRIVE: 0

EXP'D: 000000 REC'D: 100000

CZRLG DVC FTL ERR  00016 ON UNIT 00 TST 017 SUB 000 PC: 020512

WRITING RLCS MODIFIED RLBA

CONTROLLER: 174400  DRIVE: 0

EXP'D: 177776 REC'D: 177776

CZRLG DVC FTL ERR  00021 ON UNIT 00 TST 019 SUB 000 PC: 021050

WRITING RLDA MODIFIED RLBA

CONTROLLER: 174400  DRIVE: 0

EXP'D: 177776 REC'D: 177776

CZRLG DVC FTL ERR  00211 ON UNIT 00 TST 020 SUB 000 PC: 021216

WRITING RLMP MODIFIED RLBA

CONTROLLER: 174400  DRIVE: 0

EXP'D: 177776 REC'D: 177776

CZRLG DVC FTL ERR  00203 ON UNIT 00 TST 022 SUB 000 PC: 021540

NOOP(0) MODIFIED RLBA

CONTROLLER: 174400  DRIVE: 0

EXP'D: 002416 REC'D: 112416

CZRLG EOP    1

    8 TOTAL ERRS

• It looks like the MSB in the BA register is stuck on.  We will need to replace E50, a National Semiconductor DS8556 to fix it.

• Cully's RL11 has a broken 5k trimpot, so we need to replace that before we can try it.

• We borrowed an RL11 from a DEC PDP-11/34 in the warehouse. We ran the ZRLGE0 diagnostic. It ran for a while and then the light pattern on the console froze. We halted the processor and the address was 15702. This is in a routine that writes to the CS register. The calling address in R5 was 21640.

• We are stuck in a microcode loop at addresses 006, 015, 012, 020, 021, 014, 022, 023, 006 over and over. The notes in the microcode word 012 say Await Bus Busy. Maybe the RL11 is not gaining control of the Unibus?

• We swapped the locations of the RL11 and the Unibone so that the Unibone is behind the RL11. The Unibone can't DMA the MSCP bootloader into the PDP-11/40's memory so we have a problem with bus grants.

2/11/26

• DDS, one of the wizards on the FCF DEC forum suggested that the magnetic field from the transformer in the RX02 diskette drive mounted above the RL02 disk drive was affecting the disk drive. We power up the 11/40 and spun-up the RL02 drive when it was in the extended position. We confirmed that the READY light flickers when the drive is pushed about half way into the cabinet. We unplugged the power cord for the RX02 and confirmed that the READY light does not flicker as RL02 disk drive is pushed all the way into the rack.

• We will swap the positions of the TU60 cassette drive and the RX02 diskette drive to eliminate the interference from the RX02 power supply transformer.

• We removed all of the Unibus boards that were in the 9-slot expansion backplane and removed the backplane.

• The NPR L signal should be bussed from pin AS2 on Unibus slot 1 to pin FJ1 on all MUD and SPC slots and then to pin AS2 on the Unibus slot 9.

  • Closely check the NPG wiring from slot to slot. The NPG H signal should go from pin AU1 on Unibus slot 1 to NPG-IN H on pin CA1 on the first SPC slot. All of the slots should have a jumper from NPG-IN H on pin CA1 to NPG-OUT H on pin CB1.  In this backplane the CA1-CB1 jumpers have been removed on slots 5 & 7. The NPG-OUT H on pin CB1 of each slot should be wired to NPG-IN H on pin CA1 on the next down steam slot. Finally SPC slot 9 should have NPG-OUT H on pin CB1 wired to NPG H signal on pin AU1 on Unibus slot 9.

• All of the NPR and NPG wiring looks OK.

• The RL11 controller that we are using now was borrowed from the PDP-11/34 in the warehouse. The RL02 disks worked OK in that system, but the RK05 disks did not work. Maybe this RL11 controller is not driving the NPG-OUT H signal? That would explain the problem with the Unibone when it is downstream of the RL11.

• When the RL11 does an interrupt it drives the Unibus BR5 signal low, the processor responds with a BG5 H signal, the RL11 responds with a SACK driven low. The RL11 monitors the BBSY L signal from the processor, and when it goes high the RL11 drives BBSY L low to take ownership of the Unibus. The interrupt vector is 160.

• It looks like the state of the NPG signal from the processor never changes. That will be our debug project for Saturday.

2/14/26

• • We put the processor timing board on an extender and looked at the D, C, 0, and 1 pins on the 74H74 E27 with the oscilloscope. We can see lots of clock pulses, the D input is always high so the 0 output is always high and the 1 output is always low. 

  • We ran the MSCP XXDP script on the Unibone. Part of the script loads the MSCP bootloader into memory @ 010000. The Unibone uses DMA to write to memory. When we run the "m ll" command in the demo tool we can see the Unibone do an NPR for 750ns and see the NPR flip-flop change state every 15us.

  • We changed one of the 'scope probes to look at the BUS NPG H signal on pin 10 of the DEC8881 E42. The BUS NPG H signal should go high when the NPR flip-flip changes state. We can see the K4-5 NPR (1) L input signals to the 8881 change state, but there is no corresponding state change on the 8881 output on pin 10, BUS NPG H. Something is holding the BUS NPG H signal low all of the time.

  • We removed the Unibone and replaced it with a jumper board. We spun up the RL01 and tried to boot from it. We can see lots of NPR requests from the RL11, and the BUS NPG H signal never goes high.

  • The BUS NPG H signal from the Timing board is on processor backplane pin C07P2 and goes to A09U1. We measured 50 Ohms to ground on the BUS NPG H. We pulled the M9202 Unibus jumper and the resistance went infinite. We removed the RL11 and RX211 controllers, and reinstalled the M9202 Unibus jumper. The resistance went to a few Megaohms.

  • We put a grant jumper board in place of the RX211 controller and reinstalled the Unibone and RL11 controllers. We powered on the system, spun up the RL02, booted ODT, and tried to boot from the RL02. We could see the BUS NPG H changing state, so that issue is fixed. It still doesn't boot because the disk pack probably doesn't have a boot block on it.

  • We used PDP-11 GUI to write a partial disk image to the RL02 through the serial console. It was working, but we were not willing to wait hours for it to finish. The partial image booted and went into space.

  • We booted XXDP from the emulated RA80 on the Unibone and ran the RLG diagnostic. It failed saying that the RL11 controller is not interrupting. We will have to do more testing to determine if this is a RL11 controller problem, or a processor problem.

.R ZRLG??

ZRLGE0.BIC

DRSSM-F0

CZRLG-E-0

CZRLG TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11=1, RLV11=2, RLV12=3 (O)  ? 1

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

CZRLG DVC FTL ERR  00022 ON UNIT 00 TST 023 SUB 000 PC: 021652

NO INTERRUPT FROM NOOP(0)

CONTROLLER: 174400  DRIVE: 0

BEFORE COMMAND: CS: 000301 BA: 002416 DA: 000001 MP: 000000

TIME OF ERROR:  CS: 000301 BA: 002416 DA: 000001 MP: 000000?

CZRLG DVC FTL ERR  00204 ON UNIT 00 TST 024 SUB 000 PC: 022002

INTERRUPT PRIORITY FAILURE

CONTROLLER: 174400  DRIVE: 0

AT PROCESSOR LEVEL 000200

CZRLG DVC FTL ERR  00028 ON UNIT 00 TST 026 SUB 000 PC: 022142

GET STATUS WOULD NOT INTERRUPT

CONTROLLER: 174400  DRIVE: 0

BEFORE COMMAND: CS: 000305 BA: 002416 DA: 000003 MP: 000235

TIME OF ERROR:  CS: 000305 BA: 002416 DA: 000003 MP: 000235?

CZRLG DVC FTL ERR  00030 ON UNIT 00 TST 028 SUB 000 PC: 022402

OPI WOULD NOT GENERATE INTERRUPT

CONTROLLER: 174400  DRIVE: 0

BEFORE COMMAND: CS: 102305 BA: 002416 DA: 000001 MP: 000235

TIME OF ERROR:  CS: 102305 BA: 002416 DA: 000001 MP: 000235?

CZRLG DVC FTL ERR  00035 ON UNIT 00 TST 030 SUB 000 PC: 022544

READ HEADER WOULD NOT INTERRUPT

CONTROLLER: 174400  DRIVE: 0

BEFORE COMMAND: CS: 000311 BA: 002416 DA: 000001 MP: 044004

TIME OF ERROR:  CS: 000311 BA: 002416 DA: 000001 MP: 000034?

CZRLG DVC FTL ERR  00040 ON UNIT 00 TST 036 SUB 000 PC: 023606

SEEK WOULD NOT INTERRUPT

CONTROLLER: 174400  DRIVE: 0

BEFORE COMMAND: CS: 000307 BA: 002416 DA: 000205 MP: 110007

TIME OF ERROR:  CS: 000306 BA: 002416 DA: 000205 MP: 110007?

CZRLG EOP    1

    6 TOTAL ERRS

• • We ran the RLH diagnostic and it reported the same issues with interrupts not working.

.R ZRLH??

ZRLHB1.BIC

DRSSM-F0

CZRLH-B-0

CZRLH TESTS WRITE DATA, READ DATA, AND WRITE CHECK OPERATIONS

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11 (L) Y ? Y

BUS ADDRESS (O)  174400 ?

DRIVE TYPE = RL01 (L) Y ?

VECTOR (O)  160 ?

BR LEVEL (O)  5 ?

DRIVE (O)  0 ?

CHANGE SW (L)  ? N

CZRLH DVC FTL ERR  00004 ON UNIT 00 TST 002 SUB 000 PC: 016512

NO INTRPT ON WRT OP

CNTRLR: 174400 DRV 0

BEFORE COMMAND: CS: 000313 BA: 003426 DA: 000000 MP: 154003

TIME OF ERROR:  CS: 000313 BA: 004026 DA: 000001 MP: 010421 010421 010421

CZRLH DVC FTL ERR  00024 ON UNIT 00 TST 006 SUB 000 PC: 017266

NO INTRPT WITH HDR NT FND FORCED

CNTRLR: 174400 DRV 0

BEFORE COMMAND: CS: 000313 BA: 003426 DA: 000050 MP: 154003

TIME OF ERROR:  CS: 112313 BA: 003430 DA: 000050 MP: 000400 000400 000400

• • We tried the original RL11 controller. This one works much better.

.R ?RLG??

NRLGA0.BIC

DRSSM-F0

CNRLG-A-0

CNRLG TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11=1, RLV11=2, RLV12=3 (O)  1 ? 1

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

CNRLG EOP    1

    0 TOTAL ERRS

CNRLG EOP    2

    0 TOTAL ERRS

CNRLG EOP    3

    0 TOTAL ERRS

.R ?RLH??

ZRLHB1.BIC

DRSSM-F0

CZRLH-B-0

CZRLH TESTS WRITE DATA, READ DATA, AND WRITE CHECK OPERATIONS

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11 (L) Y ?

BUS ADDRESS (O)  174400 ?

DRIVE TYPE = RL01 (L) Y ? N

VECTOR (O)  160 ?

BR LEVEL (O)  5 ?

DRIVE (O)  0 ?

CHANGE SW (L)  ? N

CZRLH EOP    1

    0 TOTAL ERRS

CZRLH EOP    2

    0 TOTAL ERRS

.R ?RLI??

ZRLID1.BIN

DRSSM-F0

CZRLI-D-0

CZRLI TESTS THE RL01-02 INTERFACE AND BASIC DRIVE LOGIC

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? QQ1

UNIT 0

RL11 (L) Y ?

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

CZRLI EOP    1

    0 TOTAL ERRS

CZRLI EOP    2

    0 TOTAL ERRS

CZRLI EOP    3

    0 TOTAL ERRS

.R ?RLJ??

ZRLJB2.BIC

DRSSM-F0

CZRLJ-B-0

CZRLJ TESTS OUTER & INNER GUARD BAND DETECTION AND SEEK OPERATIONS

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11 (L) Y ? Y

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

CZRLJ EOP    1

    0 TOTAL ERRS

CZRLJ EOP    2

    0 TOTAL ERRS

.R ?RLK??

ZRLKB3.BIC

DRSSM-F0

CZRLK-B-0

CZRLK PERFORMS RANDOM OPERATIONS OF GET STATUS, SEEK, READ, AND WRITE

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11 (L) Y ?

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

WRITING PACK TIME: 00:00:00 RLCS: 174400 DRIVE: 0 DRIVE TYPE = RL02

TESTING STARTED

We let this one run for an hour and then stopped it. No errors were reported.

.R ?RLN??

ZRLNB0.BIC

DRSSM-F0

CZRLN-B-0

CZRLN TESTS SEEK & ROTATIONAL TIMING AND WRITE & READ DATA

UNIT IS RL01,RL02

RSTRT ADR 145676

DR>STA

CHANGE HW (L)  ? Y

# UNITS (D)  ? 1

UNIT 0

RL11 (L) Y ?

BUS ADDRESS (O)  174400 ?

VECTOR (O)  160 ?

DRIVE (O)  0 ?

DRIVE TYPE = RL01 (L) Y ? N

BR LEVEL (O)  5 ?

CHANGE SW (L)  ? N

TEST 1 CANNOT BE PERFORMED...P-CLOCK IS NOT AVAILABLE

RESOLUTION OF A P-CLOCK IS REQUIRED TO MEASURE SEEK TIME

TEST 4 CANNOT BE PERFORMED...P-CLOCK IS NOT AVAILABLE

RESOLUTION OF A P-CLOCK IS REQUIRED TO MEASURE ROTATIONAL TIMING

CZRLN EOP    1

    0 TOTAL ERRS

• • Mike brought some RL02 packs from his collection. RT11 booted OK

RT11

000000 000000 001230 000046

@DL

RT-11XM (S) V05.00

.SET TT QUIET

WELCOME TO THE RT-11 COMPUTER SYSTEM

***PLEASE ENTER TODAY'S DATE***

DATE DD-MMM-YY

XXDP+

000770 000000 002102 000000

@DL

   Starting XXDP Extended Monitor.

   For general help, type     HELP

   For help with the Quickware diagnostics, type   TYPE QHELP.TXT

   Enter today's date,   I.E.    DA 25-JAN-87

2/18/26

• Remove the NPG-in to NPG-out jumper on the backplane for a convenient slot and install the RX211. Run diagnostics on the RX211 Diskette controller and the RX02 Diskette drives.

  • Take pictures of the EIS and FIS boards so we can determine what revision level they are. There is a giant ECO for the EIS board. The EIS diags check for the ECO.

To Do:

• Add a second RL02 drive.

• Make bootable RL02 packs for RT11, RSX11, RSTS, UNIX, and any other OS that might be interesting.

• Swap positions of the RX02 and TU60 to avoid the magnetic field from the RX02 interfering with the RL02.

• Add a working RX211 controller for the RX02.

• Add a TA11 controller for the TU60.

• Connect the VT11 backplane and see if any of the VT11 works. Connect the VR14 and see if that works.

• Connect the TC11 and TU56-H and see if that works.

• Add a DZ11 and connect it to the breakout panel.

• Add the LK10 controller and the LK11 button box.

• Add a KW11-P programmable clock.

• Make a TC11 boot ROM for the M9312.

• Add a light pen to the VR14 and see if we can get Moon Lander to work.

• Try the collection of GT40/GT44 software to see if anything would make an interesting demonstration.

PDP-11/40 Diagnostics

KD11-A PDP-11/40 Processor
MAINDEC-11-ZKDMD0.BIC 1140/1135 T14 Traps Test 14-Feb-26
MAINDEC-11-ZKMAA0.BIN 1140/1135 Basic Memory Timing 14-Feb-26

MAINDEC-11-BQAAA0.BIC 1140/1135 Watchdog Timer

MAINDEC-11-BQEAC1.BIC 1140/1135 KD11-A CPU Diagnostic 14-Jan-26
MAINDEC-11-EQKCE1.BIC 1140/1145/1160/1165 Instruction Exerciser 24-Jan-26

MAINDEC-11-ZKAQH0.BIC PDP-11 Power Fail

MAINDEC-11-DCKBR-E-PB 11/40-11/45 CPU PARITY TEST

KT11-D Memory Management

MAINDEC-11-BKTAD1.BIC 1140/1135 KT11-D Basic Logic Test 28-Jan-26

MAINDEC-11-BKTBB0.BIC 1140/1135 KT11-D Access Keys Test 28-Jan-26

MAINDEC-11-BKTCB0.BIC 1140/1135 KT11-D Moves 28-Jan-26

MAINDEC-11-BKTDC0.BIC 1140/1135 KT11-D Processor States Test 28-Jan-26

MAINDEC-11-BKTFD0.BIC 1140/1135 KT11-D Abort 28-Jan-26

MAINDEC-11-BKTGD1.BIC 1140/1135 KT11-D Exerciser 28-Jan-26

KW11-E EIS

Maindec-11-DCKBI-A-D ASH Instruction Test 14-Jan-26

Maindec-11-DCKBJ-A-D ASHC Instruction Test 14-Jan-26

Maindec-11-DCKBK-A-D MUL Instruction Test 14-Jan-26

Maindec-11-DCKBL-A-D DIV Instruction Test 14-Jan-26

Maindec-11-DCQKA-A-D MUL/DIV Exerciser 14-Jan-26

Maindec-11-ZKEBB0 1135/1140 KE11 EAE Basic Logic Test
Maindec-11-ZKECA0 1135/1140 EAE Random Exerciser

KW11-F FIS

Maindec-11-DBKEA-A-D FIS Instruction Test 14-Jan-26

Maindec-11-DBKEB-A-D FIS Instruction Exerciser 17-Jan-26

KW11-L Line Time Clock

Maindec-11-DZKWA-A-D KW11-L Line Frequency Clock 17-Jan-26
Maindec-11-CZKWA-G-O KW11-L Line Frequency Clock AK-8875G-MC 14-Feb-26

KJ11-A  Stack Limit Option
Maindec-11-DCKBF-B-D KJ11-A Stack Limit Test 24-Jan-26

DZ11 8 Line Asynchronous Multiplexer

Maindec-11-DZDZA-E-PB DZ11 8 Line Asynchronous Multiplexer Tests
Maindec-11-CZDZAG0 DZ11 Asynchronous Multiplexer Test

LK11 Bush Button Box

Maindec-11-DZLKA-A LK11A Push Button Module Diagnostic

MS11-LD 128kW MOS Parity Memory

Maindec-11-ZQMBG2.BIN 0-124K Memory Exerciser 8K

Maindec-11-ZQMCH0.BIC 0-124K Memory Exerciser 16K, Parity Traps are disabled, so it will not run.

M9312 Boot/Terminator

Maindec-11-ZM9BE0.BIC M9312 Boot Terminator 17-Jan-26

DEUNA/DELUA Ethernet

Maindec-11-ZUAA DEUNA REPAIR DIAGNOSTIC

Maindec-11-ZUAB DEUNA - PDP11 FUNCTIONAL DIAGNOSTIC

Maindec-11-ZUACD0.BIC DEUNA,DELUA NI EXERCISER

Maindec-11-ZUADB1.BIC DELUA - PDP11 FUNCTIONAL DIAGNOSTIC

RL11/RL02 Disk Controller and Drive

MAINDEC-11-ZRLGE0.BIC RL11/RLV11 Controller #1, TESTS CONTROLLER FUNCTIONS, INTERFACE LOGIC, REGISTER OPERATION, 14-Feb-26
MAINDEC-11-ZRLHB1.BIC RL11/RLV11 Controller #2, TESTS WRITE DATA, READ DATA, AND WRITE CHECK OPERATIONS, 14-Feb-26
MAINDEC-11-ZRLID1.BIC RL01/RL02 Drive Test #1, TESTS THE RL01-02 INTERFACE AND BASIC DRIVE LOGIC, 14-Feb-26
MAINDEC-11-ZRLJC0.BIC RL01/RL02 Drive Test #2, TESTS OUTER & INNER GUARD BAND DETECTION AND SEEK OPERATIONS, 14-Feb-26
MAINDEC-11-ZRLKB3.BIC RL01/RL02 Performance Exerciser, PERFORMS RANDOM OPERATIONS OF GET STATUS, SEEK, READ, AND WRITE, 14-Feb-26
MAINDEC-11-ZRLLC1.BIN RL01/RL02 Drive Compatibility, VERIFIES INTERCHANGEABILITY OF CARTRIDGES BETWEEN DRIVES
MAINDEC-11-ZRLMC0.BIN RL01/RL02 Bad Sector File Test, A UTILITY PROGRAM FOR FORMATTING BAD SECTOR FILES
MAINDEC-11-ZRLNC0.BIN RL01/RL02 Drive Test #3, TESTS SEEK, ROTATIONAL TIMING AND WRITE & READ DATA, 14-Feb-26

RX211/RX02 Diskette Controller and Drive

MAINDEC-11-ZRXAF0.BIC RX11 System Reliability Test
MAINDEC-11-ZRXBF0.BIC RX11 Interface Diagnostic
MAINDEC-11-ZRXCA0.BIN RX02 Performance Exerciser
MAINDEC-11-ZRXDC0.BIC RX02 Subsystem Verify
MAINDEC-11-ZRXEA2.BIC RX02 Formatter
MAINDEC-11-ZRXFB0.BIC RX02 Functional Controller

TA11/TU60 DECassette  Controller and Drives
MAINDEC-11-ZTAAC0.BIN TA11 Logic Test #1

MAINDEC-11-ZTABC0.BIN TA11 Logic Test #2

MAINDEC-11-ZTACC0.BIN TA11 Manual Intervention

MAINDEC-11-ZTADD0.BIN TA11 Motion Test

MAINDEC-11-ZTAEC0.BIC TA11 Data Reliability

MAINDEC-11-ZTAFC0.BIN TA11 Cassette Absolute Loader

MAINDEC-11-ZTAHA0.BIN TA11 Cassette Duplicator

TC11/TU56 DECtape Controller and Drive

MAINDEC-11-ZTCAA0.BIC TU56/TC11 TC1 Basic Logic

MAINDEC-11-ZTCBE0.BIC TU56/TC11 TC2 Basic Logic

MAINDEC-11-ZTCCA0.BIC TU56/TC11 TC3 Basic Logic

MAINDEC-11-ZTCDC0.BIC TU56/TC11 TC4 Basic Logic

MAINDEC-11-ZTCED0.BIC TU56/TC11 TC5 Basic Logic
MAINDEC-11-YPTCB0.BIN TC11 DecTape Formatter

VT11 Graphics

MAINDEC-11-DGTAD2.BIN GT40 Instruction Test 1

MAINDEC-11-DGTBD0.BIN GT40 Instruction Test 2

MAINDEC-11-DGTCC0.BIC GT40 Visual Test

MAINDEC-11-DGTDD0.BIN GT40 Rom Verify

MAINDEC-11-DGTED0.BIN GT40 Quick Verify

MAINDEC-11-DGTGB0.BIC GT40/GT44 Visual Display Test

Ultrix-11 Notes:

Set the terminal to 9600, E71

Use lower case to login or else it will always use upper case

Default Maintenance Userid/Password is; field/service
To shutdown Ultrix: From the root user, /etc/shutdown -h now
To boot Ultrix: @dl

ODT Notes:

L Set the address

E Examine the previously set address

D Deposit data in the previously set address

G Start execution at the previously set address

/ Open an address or register for modification

CR Close an open location

LF Closes an open location and opens the next location

Rx Open a register

P Resume execution

^S Display a portion of memory

RL02 Notes:

Vector Address: 160

Base Address: 774400

Priority Level: 5

Programmer's Console Cable Connections

Repairs:

• 11/24/25 Replaced the SN74153 E38 on the M7231 Data Paths board to fix a stuck bit-10 data problem.

• 12/31/25 Replaced the SN74H20 E66 on the M7233 IR Decode board to fix the HALT instruction.

• 1/10/26 Fix a broken trace for the K3-3 IR (14:12)=0 L signal under E38 on the M7233 IR Decode board to fix the SWAB instruction.

To Do:

• Install jumper W5 on the M7234 Timing board because we don't have core memory. (Done 28-Dec-25)

• Replace the modified filler panel below the front console with a normal filler panel. (Done 29-Oct-25)

• Replace the damaged KY11-D Programmer's Console with an undamaged one. The old and new chassis have different Programmer's Consoles and mounting brackets. The power enable wires connect to the left side on the old design and to the right on the new design. (Done 29-Oct-25)

• Remove the non-DEC power supplies that are mounted to the rear swing frame. (Done 29-Oct-25)

• Remove the PDP-11/23 boards and Q-Bus backplane from the CPU cabinet. (Done 29-Oct-25)

• Remove the Tektronix RM504 oscilloscope and lab power supply from the CPU cabinet. The idea was to install this oscilloscope in the PDP-9 as a future graphics display, but we really should use an RM503. We have several RM503 oscilloscopes in the warehouse to choose from. (Done 29-Oct-25)

• It might be a good idea to use one of the newer design CPU chassis. The newer chassis design, S/N 5000 and up, has an improved power distribution system. We have the three of newer chassis. One is in an empty cabinet, and two empty ones in the PDP-11/45 expansion cabinets. If the newer chassis is an expansion chassis, it might not have the signals for the line clock wired to the CPU backplane, or the wires that go from the Programmer's Console key switch to the AC Power Controller.

• If we use the older design chassis: (1-Nov-25 we decided to use the newer design chassis)

  • Repair or replace the first power distribution backplane.

  • Repair the first power supply to power distribution backplane connector on the power harness.

• Repair the AC power wiring for the fans in the power supply. (Done 19-Nov-25)

• Connect the terminals on the PDP-11/40 console to the remote input connector on the 861C AC Power Controller in the bottom of the cabinet. (Done 6-Dec-25)

• Test and possibly repair the AC and DC power subsystems. (Done 12-Nov-25)

• Test and possibly repair the upper and lower fans in the CPU chassis and in the power supply. Upper fan is repaired, the rear lower fan is seized.

• Install the PDP-11/40 CPU backplane and CPU boards in the CPU chassis. Leave the KD11-E EIS Option, KD11-F FIS Option, KT11-D Memory Management Option, KJ11-A Stack Limit, and Kw11-L Line Time Clock boards out of the CPU backplane for the initial testing. Note: There are a bunch of jumpers that need to be changed if these options are left out. (Done 12-Nov-25)

• Install the M9312 Bootstrap/Terminator in slot 9AB of the CPU backplane. (Done 12-Nov-25)

• Test and possibly repair the KY11-D Programmer's Console. (Done 12-Nov-25)

• Test and possibly repair the KD11-A CPU. Note: The 11/35 has another CPU board set, and Mike has another CPU board set at home. (Done 10-Jan-26)

• Test and possibly repair the DL11 Asynchronous Line Interface Board. (Done 10-Jan-26)

• Install the I/O expansion backplane in the CPU chassis. Move the M9312 to slot 16AB in the expansion backplane and install a M981 Unibus Jumper from slot 9AB to 10AB. (Done 19-Nov-25)

• Perform simple tests on the MS11-LD 128kW MOS Memory board and possibly repair it. (Tested 10-Jan-26)

• Connect a laptop to the DL11, load PDP-11 GUI and verify that the CPU, Memory, and I/O board diagnostics run OK.  (Done 10-Jan-26)

• Verify that the minimal CPU board set, the MS11-LD 128kW MOS Memory, and any of the I/O boards that are in the expansion backplane pass diagnostics.  (Done 10-Jan-26)

• Install the KD11-E EIS CPU Option in the CPU backplane and verify that it passes diagnostics. (Done 14-Jan-26)

• Install the KD11-F FIS CPU Option in the CPU backplane and verify that it passes diagnostics. (Done 14-Jan-26)

• Install the KT11-D Memory Management Option in the CPU backplane and verify that it passes diagnostics. (Done 28-Jan-26)

• Install the KJ11-A Stack Limit Option in the CPU backplane and verify that it passes diagnostics. (Done 24-jan-26)

• Install the TU60 in the top of the CPU cabinet. Install the TA11 controller in the I/O backplane and connect it to the TU60.

• Test and possibly repair the TA11 and TU60. There is lots of restoration info here.

• Install the RX02 diskette drive in the I/O cabinet. (Done 11/30/25)

• Connect the RX02 to the RX211 board. (Done 10-Jan-26)

• Create RX02 XXDP media using PDP-11 GUI and see if we can boot the XXDP Diagnostic Monitor from diskette. Note: The M9213 Bootstrap/Terminator board has the DY (RX02) boot ROM.

• Install the TU56-H DECtape drive in the I/O cabinet with the TC11 DECtape controller. (Done 11/30/25)

• Connect the TC11 to the end of the Unibus in the 11/40 chassis. Move the Unibus terminator from the CPU chassis to the TC11 chassis.

• Test and repair the TC11 and the TU56-H.

• Install two RL02 drives in the DECtape cabinet. (One done on 28-Jan-31)

• Install scratch media in the RL02 drives and run the disk drive diagnostics.

• Install XXDP or RT-11 media in one of the RL02 drives and see if the Diagnostic Monitor or Operating System will boot. (Done 14-Feb-26)

• Install the VT11 backplane and boards in the CPU chassis. Move the M9312 to slot 17BC in the expansion backplane and install a M981 Unibus Jumper from slot 16AB to 17AB.

• Install the VR14 in the CPU cabinet and leaving a 3U gap above the CPU chassis. (Done 29-Nov-25)

• Connect the VR14 to the VT11 and see if the diagnostics will run.

• Create BSD2.9 UNIX RL02 media and see if it will boot.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.  (Done 31-Jan-26)

• Connect the two RL02 disk drives to the RL11 controller.  (One done on 31-Jan-26)

• Replace the DL11 with a DZ11, connect it to the RS-232 distribution panel, and see if the diagnostics will run.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.

HALT Instruction Debugging Notes:

• • The K2-8 CLKIR (1) H signal comes from the Microcode board and enables the clock pulses on print K4-2.

  • The K2-8 CLK0FF (1) H signal comes from the Microcode board and is how the microcode turns off the processor clock. When this signal is active the Clock IDLE flip-flop (K4-2) will turn on and the Clock RUN flip-flop will turn off.

  • On page 1 of the microcode Flow Diagram, step 004 (FET04) will use BUT(INSTR 1) (BUT 37) to determine the future address. Step 005 (FET05) restores the R[PC], and then should branch to step 122 (CON00) on page 11. On page 11 we see the microcode enter the normal console code where it waits for a console button press. A CONT button press would restart the program running.

  • The IR Decode board schematic page K3-8 shows the source of the K3-8 HALT+RESET L signal.

  • The IR Decode board schematic page K3-5 shows the source of the K3-5 BUBC* (BUT37) H signals. There is a lot of random logic used to generate these signals which will take a lot of debugging if it is broken.

  • The 9-bit UPP Register on the K2 Microcode Board determines which microword will be selected in the ROMs. The address is the NOR of the BUS U [08:00], the BUBC [5:0], and the EUBC [8:1].

  • The 74174 E5 latch that makes PUPP(3:0) register on the Microword board is on sheet K2-2. The outputs should be displayed on the KM11 lights. The lights will likely display 123 or 133 when they should show 122. We can trigger the 'scope when CLK goes high and look at the inputs and outputs for K2-2 PUPP0 (1)H and K2-2 PUPP3 (1)H. Both should be low for the 122 microword address. Since the problem has been proven to be on the IR Decode board we can assume that the 

  • Microword 004 (FET04) has UBF = 037 to use BUT (INSTR 1) (BUT 37) to determine the offset to the base microcode address. At microcode address 005 the U WORD ROMS on K2 > BUS U [08:00] contains the base address of 100 in the UPF bits. The offset is from the IR REG in K3 > U BRANCH CONTROL on K3 > BUBC [5:0] (BUT XX) > BUT MUX on K3-2. The offset should be 22 but is 23 or sometimes 33 resulting in a jump to microword 123 or 133 instead of 122.

  • We need to stop the microcode at word 005 and look at the state of the BUS U [08:00] from the U Word board and the BUBC [5:0] signals from the IR Decode board. Since the IR Decode board causes the HALT problem the BUS U [08:00] signals are probably OK and the problem is really on the BUBC [5:0] signals. The input and output of the BUT MUX might be the place to look first. If the output of the BUT MUX is OK then the NOR gate to the UPP register might be broken.

  • The BUT MUX is on schematic sheet K3-2. Signal K3-2 BUBC0 (BUT37:20) L comes from the 74150 E81 on the IR Decode board. The MUX should have S0..S3 all high to select the BUBC5..0 (BUT37) H signals, and STB low to enable the chip. The K2-5 UBF4 (1) L will enable E72 and E81 to make the K3-2 BUBC0 (BUT37:20) L and K3-2 BUBC1 L signals. The 74151 E90 supplies the K3-2 BUBC3 L signal. We need to check that signal too. The K3-5 BUBC5..0 (BUT37) bits for the HALT instruction should be 010010 and are on schematic sheet K3-5. We should check the 74150 E97 to insure that the STB input is high and the f output is high.

  • The K3-5 BUBC5..0 signals go to the BUT MUX and then to the NOR gates on K2-2.

Memory Parity Traps:

• The MS11-LD memory board manual says that if bit-0 in the CSR at address 772100 is set to a 1 the memory board will drive the Unibus signal BUS PB L if there was a parity error. We should only see a parity error when we EXAM uninitialized memory, not when we DEP memory.

• Determine if the MS11-LD memory board is driving the Unibus signal BUS PB L low when we DEP to uninitialized memory. If not, then investigate why the processor microcode is branching to the TRAP ERR microcode on the microcode flow chart sheet 6 when we DEP.

Trap Debugging Notes:

• A memory parity error will set the PERR flip-flop on schematic sheet K4-3 for the Timing board. We should look at the state of the PERR flip-flop E24 on pin 8 to see if the flip-flop gets set when we DEP. If so we can work our way back through the logic to the BUS PB L signal on pin 5 of the 380 chip E1. If the Unibus signal BUS PB L is being driven low when we DEP we need to investigate the MS11-LD memory board, or disable the memory error Trap.

• Removing jumper W8 on the Status board, schematic sheet K5-5, enables the memory parity error trap. For now we should make sure that W8 is installed.

• The MS11-LD the CSR address is 772100. The MS11-L technical manual says that the parity error logic is enabled during a memory read cycle. We have not found the read enable circuitry yet. When bit-0 in the CSR is a 1 the memory board will drive the Unibus signal BUS PB L if there was a parity error. If bit-15 is of the CSR on and the red LED is on there has been a parity error. It looks like the parity checking logic will detect a parity error when writing, but should not do anything. The CSR00 H signal from bit-0 of the CSR on pin 7 of E15 (sheet 8) should be low and at pin-2 of E16 (sheet 7) and the output signal PAR ERR EN L will be high so BUS PB L (pin-AN2 on the backplane) from pin-15 E1 (sheet 2) will not be driven. Eventually we should be able to run MAINDEC-11-CZMQC to test the memory board.

SWAB Debugging Notes:

• We need to test the IR Decoders E80, E61, E31, and E11 on the IR Decoder board K3-3. The SWAB instruction format is 0003dd where dd is the register number. We have been using the instruction 000300 for SWAB R0 in our testing. This instruction should turn on signal K3-3 DM=0 L from pin 13 of the 8251 Decoder E80, K3-3 IR (08:06)=3 L from pin 10 of E61, K3-3 SM=0 L  from pin 13 of E31, and K3-3 IR (14:12)=0 L from pin 13 of E11.

• At microword 004 we have the branch (INSTR 1) or BUT(37). This adds an offset to the base address of 100 to branch to the individual instruction microcode. In this case the offset is 22 instead of 34 so the microcode is branching to address 122 HALT instead of 134 SWAB instruction.

• On sheet K3-2 of the IR Decode, microword 004 has UBF=37 to use the BUT 37 MUX inputs to determine the offset for branching. Having UBF (4:0) bits on will select the D15 input of the 74150 MUX chips. Signal K3-2 BUBC1 L is active and should not be. Signal K3-2 BUBC2 L is inactive and should be. Signal K3-2 BUBC3 L is inactive and should be.

• On the input of 74150 MUX E71, K3-5 BUBC1 (BUT37) H is active and should not be, 74151 MUX E98, K3-5 BUBC2 (BUT37) H is inactive and should be, and 74151 MUX E90, K3-5 BUBC3 (BUT37) H is inactive and should be.

• It might be easiest to look at the inputs on the 74H52 AND/OR gate E53 to determine what signals are active that should not be. Since the IR Register seems to be working correctly and contains 0000300 the input signals K3-3 IR10 (1)H and K3-3 IR04 (1)H should be inactive. That only leaves signal K3-5 I1K1 H on E53 pins 01, 02, 12, and 13 as the trouble maker. That signal comes from the 74H30 8 input NOR gate E68. We will need to look at all of the inputs to see which one is low and causing trouble.

• We should look at the K3-6 SWAB*DM0 L signal from the 74H00 NAND gate E58. That is the NAND of K3-5 SWAB H and K3-3 DM=0 L inverted. There is also a K3-5 SWAB L we should look at to make sure the 74H04 inverter E45 is working. 

RL211 Debugging Notes:

• When the RL11 needs to do DMA it drives the NPR (AS2) signal low, the processor responds by driving the NPG (AU1) signal high, and then the RL11 drives SACK (AR2) low and stops driving the NPR (AS2) signal low, the processor stops driving NPG (AU1) High. This is the end of Unibus arbitration and the RL11 will get control of the Unibus when the processor completes the existing bus cycle. The RL11 monitors BBSY (AP2), and when it goes high the RL11 drives BBSY (AP2) low indicating that it has control of the Unibus. It then drives the A17:0 L Address lines from the contents of the BA and CSR registers, drives MSYN (BV1) and C1 (BT2), and reads or drives the D15:00 signals. The slave responds by driving SSYN (BU1), the RL11 stops driving BBSY (AP2) low to relinquish the Unibus. If the slave does not respond with SSYN (BU1) there is a timeout and the RL11 stops driving MSYN (BV1).

• The Timing board schematics, sheet K4-5 have the bus arbitration circuitry.

• The NPR (1) L signal comes from pin 5 of the 74H74 flip-flop E27. The NPR (1) L signal goes to an 8881 that drives BUS NPG H signal to the Unibus.

• The failure could either be the 74H74 flip-flop or the 8881 bus driver.