PDP-11/40 #2
Restoration 2026

Back to the 2025 restoration blog.

1/3/26

• If we DEP to a register everything works OK. If we DEP to memory the processor goes into space. We stepped through the DEP microcode. The microcode went from step 072/030 to 336/317. Ashlin pointed out that these are the addresses of the TRAP ERR microcode, so maybe the memory board drove BUS PB L signal to report a memory parity error when we deposited to uninitialized memory. It should never report a parity error on a memory write.

• The MS11-LD memory board manual says that if bit-0 in the CSR is on the memory board will drive the Unibus signal BUS PB L if there was a parity error. We should only see a parity error when we EXAM uninitialized memory, not when we DEP memory.

• Determine if the MS11-LD memory board is driving the Unibus signal BUS PB L low when we DEP to uninitialized memory. If not, then investigate why the processor microcode is branching to the TRAP ERR microcode on the microcode flow chart sheet 6 when we DEP.

Trap Debugging Notes:

• A parity error will set the PERR flip-flop on schematic sheet K4-3 for the Timing board. We could look at the state of the PERR flip-flop E24 on pin 8 to see if the flip-flop gets set when we DEP. If so we can work our way back through the logic to the BUS PB L signal on pin 5 of the 380 chip E1 on the Status board.

• Removing jumper W8 on the Status board, schematic sheet K5-5, enables the memory parity error trap. For now we should make sure that W8 is installed.

Programmer's Console Cable Connections

Repairs:

• 11/24/25 Replaced the SN74153 E38 on the M7231 Data Paths board to fix a stuck bit-10 data problem.

• 12/31/25 Replaced the SN74H20 E66 on the M7233 IR Decode board to fix the HALT instruction.

To Do:

• Install jumper W5 on the M7234 Timing board because we don't have core memory

• Replace the modified filler panel below the front console with a normal filler panel. (Done 29-Oct-25)

• Replace the damaged KY11-D Programmer's Console with an undamaged one. The old and new chassis have different Programmer's Consoles and mounting brackets. The power enable wires connect to the left side on the old design and to the right on the new design. (Done 29-Oct-25)

• Remove the non-DEC power supplies that are mounted to the rear swing frame. (Done 29-Oct-25)

• Remove the PDP-11/23 boards and Q-Bus backplane from the CPU cabinet. (Done 29-Oct-25)

• Remove the Tektronix RM504 oscilloscope and lab power supply from the CPU cabinet. The idea was to install this oscilloscope in the PDP-9 as a future graphics display, but we really should use an RM503. We have several RM503 oscilloscopes in the warehouse to choose from. (Done 29-Oct-25)

• It might be a good idea to use one of the newer design CPU chassis. The newer chassis design, S/N 5000 and up, has an improved power distribution system. We have the three of newer chassis. One is in an empty cabinet, and two empty ones in the PDP-11/45 expansion cabinets. If the newer chassis is an expansion chassis, it might not have the signals for the line clock wired to the CPU backplane, or the wires that go from the Programmer's Console key switch to the AC Power Controller.

• If we use the older design chassis: (1-Nov-25 we decided to use the newer design chassis)

  • Repair or replace the first power distribution backplane.

  • Repair the first power supply to power distribution backplane connector on the power harness.

• Repair the AC power wiring for the fans in the power supply. (Done 19-Nov-25)

• Connect the terminals on the PDP-11/40 console to the remote input connector on the 861C AC Power Controller in the bottom of the cabinet.

• Test and possibly repair the AC and DC power subsystems. (Done 12-Nov-25)

• Test and possibly repair the upper and lower fans in the CPU chassis and in the power supply. Upper fan is repaired, the rear lower fan is seized.

• Install the PDP-11/40 CPU backplane and CPU boards in the CPU chassis. Leave the KD11-E EIS Option, KD11-F FIS Option, KT11-D Memory Management Option, KJ11-A Stack Limit, and Kw11-L Line Time Clock boards out of the CPU backplane for the initial testing. Note: There are a bunch of jumpers that need to be changed if these options are left out. (Done 12-Nov-25)

• Install the M9312 Bootstrap/Terminator in slot 9AB of the CPU backplane. (Done 12-Nov-25)

• Test and possibly repair the KY11-D Programmer's Console. (Done 12-Nov-25)

• Test and possibly repair the KD11-A CPU. Note: The 11/35 has another CPU board set, and Mike has another CPU board set at home.

• Test and possibly repair the DL11 Asynchronous Line Interface Board.

• Install the I/O expansion backplane in the CPU chassis. Move the M9312 to slot 16AB in the expansion backplane and install a M981 Unibus Jumper from slot 9AB to 10AB. (Done 19-Nov-25)

• Perform simple tests on the MS11-LD 128kW MOS Memory board and possibly repair it.

• Connect a laptop to the DL11, load PDP-11 GUI and verify that the CPU, Memory, and I/O board diagnostics run OK.

• Verify that the minimal CPU board set, the MS11-LD 128kW MOS Memory, and any of the I/O boards that are in the expansion backplane pass diagnostics.

• Install the KD11-E EIS CPU Option in the CPU backplane and verify that it passes diagnostics.

• Install the KD11-F FIS CPU Option in the CPU backplane and verify that it passes diagnostics.

• Install the KT11-D Memory Management Option in the CPU backplane and verify that it passes diagnostics.

• Install the KJ11-A Stack Limit Option in the CPU backplane and verify that it passes diagnostics.

• Install the TU60 in the top of the CPU cabinet. Install the TA11 controller in the I/O backplane and connect it to the TU60.

• Test and possibly repair the TA11 and TU60. There is lots of restoration info here.

• Install the RX02 diskette drive in the I/O cabinet. (Done 11/30/25)

• Connect the RX02 to the RX211 board.

• Create RX02 XXDP media using PDP-11 GUI and see if we can boot the XXDP Diagnostic Monitor from diskette. Note: The M9213 Bootstrap/Terminator board has the DY (RX02) boot ROM.

• Install the TU56-H DECtape drive in the I/O cabinet with the TC11 DECtape controller. (Done 11/30/25)

• Connect the TC11 to the end of the Unibus in the 11/40 chassis. Move the Unibus terminator from the CPU chassis to the TC11 chassis.

• Test and repair the TC11 and the TU56-H.

• Install two RL02 drives in the DECtape cabinet.

• Install scratch media in the RL02 drives and run the disk drive diagnostics.

• Install XXDP or RT-11 media in one of the RL02 drives and see if the Diagnostic Monitor or Operating System will boot.

• Install the VT11 backplane and boards in the CPU chassis. Move the M9312 to slot 17BC in the expansion backplane and install a M981 Unibus Jumper from slot 16AB to 17AB.

• Install the VR14 in the CPU cabinet and leaving a 3U gap above the CPU chassis.

• Connect the VR14 to the VT11 and see if the diagnostics will run.

• Create BSD2.9 UNIX RL02 media and see if it will boot.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.

• Connect the two RL02 disk drives to the RL11 controller.

• Replace the DL11 with a DZ11, connect it to the RS-232 distribution panel, and see if the diagnostics will run.

• Remove either the KW11-P or DR11-C from the expansion backplane and install an RL11 disk controller.

HALT Instruction Debugging Notes:

• • The K2-8 CLKIR (1) H signal comes from the Microcode board and enables the clock pulses on print K4-2.

  • The K2-8 CLK0FF (1) H signal comes from the Microcode board and is how the microcode turns off the processor clock. When this signal is active the Clock IDLE flip-flop (K4-2) will turn on and the Clock RUN flip-flop will turn off.

  • On page 1 of the microcode Flow Diagram, step 004 (FET04) will use BUT(INSTR 1) (BUT 37) to determine the future address. Step 005 (FET05) restores the R[PC], and then should branch to step 122 (CON00) on page 11. On page 11 we see the microcode enter the normal console code where it waits for a console button press. A CONT button press would restart the program running.

  • The IR Decode board schematic page K3-8 shows the source of the K3-8 HALT+RESET L signal.

  • The IR Decode board schematic page K3-5 shows the source of the K3-5 BUBC* (BUT37) H signals. There is a lot of random logic used to generate these signals which will take a lot of debugging if it is broken.

  • The 9-bit UPP Register on the K2 Microcode Board determines which microword will be selected in the ROMs. The address is the NOR of the BUS U [08:00], the BUBC [5:0], and the EUBC [8:1].

  • The 74174 E5 latch that makes PUPP(3:0) register on the Microword board is on sheet K2-2. The outputs should be displayed on the KM11 lights. The lights will likely display 123 or 133 when they should show 122. We can trigger the 'scope when CLK goes high and look at the inputs and outputs for K2-2 PUPP0 (1)H and K2-2 PUPP3 (1)H. Both should be low for the 122 microword address. Since the problem has been proven to be on the IR Decode board we can assume that the 

  • Microword 004 (FET04) has UBF = 037 to use BUT (INSTR 1) (BUT 37) to determine the offset to the base microcode address. At microcode address 005 the U WORD ROMS on K2 > BUS U [08:00] contains the base address of 100 in the UPF bits. The offset is from the IR REG in K3 > U BRANCH CONTROL on K3 > BUBC [5:0] (BUT XX) > BUT MUX on K3-2. The offset should be 22 but is 23 or sometimes 33 resulting in a jump to microword 123 or 133 instead of 122.

  • We need to stop the microcode at word 005 and look at the state of the BUS U [08:00] from the U Word board and the BUBC [5:0] signals from the IR Decode board. Since the IR Decode board causes the HALT problem the BUS U [08:00] signals are probably OK and the problem is really on the BUBC [5:0] signals. The input and output of the BUT MUX might be the place to look first. If the output of the BUT MUX is OK then the NOR gate to the UPP register might be broken.

  • The BUT MUX is on schematic sheet K3-2. Signal K3-2 BUBC0 (BUT37:20) L comes from the 74150 E81 on the IR Decode board. The MUX should have S0..S3 all high to select the BUBC5..0 (BUT37) H signals, and STB low to enable the chip. The K2-5 UBF4 (1) L will enable E72 and E81 to make the K3-2 BUBC0 (BUT37:20) L and K3-2 BUBC1 L signals. The 74151 E90 supplies the K3-2 BUBC3 L signal. We need to check that signal too. The K3-5 BUBC5..0 (BUT37) bits for the HALT instruction should be 010010 and are on schematic sheet K3-5. We should check the 74150 E97 to insure that the STB input is high and the f output is high.

  • The K3-5 BUBC5..0 signals go to the BUT MUX and then to the NOR gates on K2-2.